Intel D425 AU80610006252AA User Manual

78  

Datasheet  

B/D/F/Type: 0/0/0/MCHBAR 

Address Offset: 

269-26Eh 

Default Value: 

241830000C30h 

Access: 

 RW; RO; 

Size: 48 

bits 

Settings to configure the DRAM refresh controller.   

 

 

47 RO  0b Core 

46:44 RW  010b  Core 

Initial Refresh Count (sd0_cr_init_refrcnt):  
Specifies the initial refresh count value.  

43:38 RW 010000b 

Core 

Direct Rcomp Quiet Window (DIRQUIET):  
This configuration setting indicates the amount 
of refresh_tick events to wait before the service 
of rcomp request in non-default mode of 
independent rank refresh. 

37:32 RW 011000b 

Core 

Indirect Rcomp Quiet Window 
(INDIRQUIET):  
This configuration setting indicates the amount 
of refresh_tick events to wait before the service 
of rcomp request in non-default mode of 
independent rank refresh. 

31:27 RW  00110b Core 

Rcomp Wait (RCOMPWAIT):  
This configuration setting indicates the amount 
of refresh_tick events to wait before the service 
of rcomp request in non-default mode of 
independent rank refresh.    

26 RW  0b Core 

ZQCAL Enable (ZQCALEN):  
This bit enables the DRAM controller to issue 
ZQCAL   S command periodically. 
 

25 RW  0b Core 

Refresh Counter Enable (REFCNTEN):  
This bit is used to enable the refresh counter to 
count during times that DRAM is not in self-
refresh, but refreshes are not enabled.  Such a 
condition may occur due to need to reprogram 
DIMMs following DRAM controller switch. 
This bit has no effect when Refresh is enabled 
(i.e. there is no mode where Refresh is enabled 
but the counter does not run) So, in conjunction 
with bit 23 REFEN, the modes are: 
REFEN:REFCNTEN --  Description  0:0 -- Normal 

refresh disable  0:1 -- Refresh disabled, but 

counter is accumulating refreshes.  1:X -- 

Normal refresh enable. 

24 RW  0b Core