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Intel D425 AU80610006252AA User Manual

Product codes
AU80610006252AA
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Processor Configuration Registers 
 
 
 
88  
 
Datasheet  
Bit Access Default 
Value 
RST/
PWR 
Description 
Control initialization. It is set by default on 
Reset, as well as whenever the corresponding 
Virtual Channel is Disabled or the Link is in the 
DL_Down state.   It is cleared when the link 
successfully exits the FC_INIT2 state.   BIOS 
Requirement: Before using a Virtual Channel, 
software must check whether the VC 
Negotiation Pending fields for that Virtual 
Channel are cleared in both Components on a 
Link. 
0 RO  0b Core 
Reserved () 
1.7.8 
DMIVC1RCAP - DMI VC1 Resource Capability 
B/D/F/Type: 0/0/0/DMIBAR 
Address Offset: 
1C-1Fh 
Default Value: 
00008001h 
Access:  
RO; 
Size: 32 
bits 
 
Bit Access Default 
Value 
RST/
PWR 
Description 
31:24 RO 
00h  Core 
Reserved for Port Arbitration Table Offset 
(RESERVED () 
23 RO  0b Core 
Reserved (RESERVED () 
22:16 RO 
00h  Core 
Reserved for Maximum Time Slots 
(RESERVED ()) 
15 RO  1b Core 
Reject Snoop Transactions (REJSNPT):  
0: Transactions with or without the No Snoop bit 
set within the TLP header are allowed on this VC. 
1: When Set, any transaction for which the No 
Snoop attribute is applicable but is not Set 
within the TLP Header will be rejected as an 
Unsupported Request. 
14:8 RO  00h Core 
Reserved () 
7:0 RO  01h Core 
Port Arbitration Capability (PAC):  
  Having only bit 0 set indicates that the only 
supported arbitration scheme for this VC is non-
configurable hardware-fixed.