Intel D425 AU80610006252AA User Manual

Datasheet 

 89 

B/D/F/Type: 0/0/0/DMIBAR 

Address Offset: 

20-23h 

Default Value: 

01000000h 

Access: 

 RW; RO; 

Size: 32 

bits 

Controls the resources associated with PCI Express Virtual Channel 1. 

 

 

31 RW  0b Core 

Virtual Channel 1 Enable (VC1E):  
0: Virtual Channel is disabled. 
1: Virtual Channel is enabled. See exceptions 
below. 
Software must use the VC Negotiation Pending 
bit to check whether the VC negotiation is 
complete. When VC Negotiation Pending bit is 
cleared, a 1 read from this VC Enable bit 
indicates that the VC is enabled (Flow Control 
Initialization is completed for the PCI Express 
port). A 0 read from this bit indicates that the 
Virtual Channel is currently disabled. 
 BIOS Requirement: 
1. To enable a Virtual Channel, the VC Enable 
bits for that Virtual Channel must be set in both 
Components on a Link. 
2. To disable a Virtual Channel, the VC Enable 
bits for that Virtual Channel must be cleared in 
both Components on a Link. 
3. Software must ensure that no traffic is using 
a Virtual Channel at the time it is disabled. 
4. Software must fully disable a Virtual Channel 
in both Components on a Link before re-
enabling the Virtual Channel. 

30:27 RO 

0h  Core 

26:24 RW  001b  Core 

Virtual Channel 1 ID (VC1ID):  
Assigns a VC ID to the VC resource. Assigned 
value must be non-zero. This field cannot be 
modified when the VC is already enabled. 

23:20 RO 

0h  Core 

19:17 RW  000b  Core 

Port Arbitration Select (PAS):  
Configures the VC resource to provide a 
particular Port Arbitration service. Valid value 
for this field is a number corresponding to one 
of the asserted bits in the Port Arbitration 
Capability field of the VC resource.    

16:8 RO  000h Core