Intel D425 AU80610006252AA User Manual

92  

Datasheet  

BIOS Requirement:  Must be initialized 
according to guidelines in the PCI Express* 
Isochronous/Virtual Channel Support Hardware 
Programming Specification (HPS). 

15:8 RO  02h Core 

Number of Link Entries (NLE):  
Indicates the number of link entries following 
the Element Self Description. This field reports 2 
(one for MCH egress port to main memory and 
one to egress port belonging to SouthBridge on 
other side of internal link). 

7:4 RO  0h Core 

3:0 RO  2h Core 

Element Type (ETYP):  
Indicates the type of the Root Complex 
Element.   Value of 2 h represents an Internal 

Root Complex Link (DMI). 

B/D/F/Type: 0/0/0/DMIBAR 
Address Offset: 

50-53h 

Default Value: 

00000000h 

Access: 

 RWO; RO; 

Size: 32 

bits 

First part of a Link Entry which declares an internal link to another Root Complex 
Element. 

 

 

31:24 RWO 

00h  Core 

Target Port Number (TPN):  
Specifies the port number associated with the 
element targeted by this link entry (egress port 
of SouthBridge). The target port number is with 
respect to the component that contains this 
element as specified by the target component 
ID. This can be programmed by BIOS, but the 
default value will likely be correct because the 
DMI RCRB in the SouthBridge will likely be 
associated with the default egress port for the 
SouthBridge meaning it will be assigned port 
number 0. 

23:16 RWO 

00h  Core 

Target Component ID (TCID):  
Identifies the physical component that is 
targeted by this link entry. BIOS Requirement:  
Must be initialized according to guidelines in the 
PCI Express* Isochronous/Virtual Channel 
Support Hardware Programming Specification 
(HPS). 

15:2 RO  0000h Core