Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
93
Bit Access Default
Value
RST/
PWR
Description
1 RO 0b Core
Link Type (LTYP):
Indicates that the link points to memory-
mapped space (for RCRB). The link address
specifies the 64-bit base address of the target
RCRB.
Indicates that the link points to memory-
mapped space (for RCRB). The link address
specifies the 64-bit base address of the target
RCRB.
0 RWO 0b Core
Link Valid (LV):
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
1.7.14
DMILE1A - DMI Link Entry 1 Address
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
58-5Fh
Default Value:
0000000000000000h
Access:
RO; RWO;
Size: 64
bits
Second part of a Link Entry which declares an internal link to another Root Complex
Element.
Element.
Bit Access Default
Value
RST/
PWR
Description
63:36 RO 0000000h
Core
Reserved ()
Reserved for Link Address high order bits.
Reserved for Link Address high order bits.
35:12 RWO 000000h Core
Link Address (LA):
Memory mapped base address of the RCRB that
is the target element (egress port of
SouthBridge) for this link entry.
Memory mapped base address of the RCRB that
is the target element (egress port of
SouthBridge) for this link entry.
11:0 RO 000h Core
Reserved (RESERVED ()