Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
96
Datasheet
1.7.18
DMILCAP - DMI Link Capabilities
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
84-87h
Default Value:
00012C41h
Access:
RO; RWO;
Size: 32
bits
Indicates DMI specific capabilities.
Bit Access Default
Value
RST/
PWR
Description
31:18 RO 0000h Core
Reserved ()
17:15 RWO 010b Core
L1 Exit Latency (L1SELAT):
Indicates the length of time this Port requires
to complete the transition from L1 to L0. The
value 010 b indicates the range of 2 us to less
than 4 us.
000: Less than 1 µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs-64 µs
111: More than 64 µs
Both bytes of this register that contain a portion
of this field must be written simultaneously in
order to prevent an intermediate (and
undesired) value from ever existing.
Indicates the length of time this Port requires
to complete the transition from L1 to L0. The
value 010 b indicates the range of 2 us to less
than 4 us.
000: Less than 1 µs
001: 1 µs to less than 2 µs
010: 2 µs to less than 4 µs
011: 4 µs to less than 8 µs
100: 8 µs to less than 16 µs
101: 16 µs to less than 32 µs
110: 32 µs-64 µs
111: More than 64 µs
Both bytes of this register that contain a portion
of this field must be written simultaneously in
order to prevent an intermediate (and
undesired) value from ever existing.
14:12 RWO 010b Core
L0s Exit Latency (L0SELAT):
Indicates the length of time this Port requires to
complete the transition from L0s to L0.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs-4 µs
111: More than 4 µs
Indicates the length of time this Port requires to
complete the transition from L0s to L0.
000: Less than 64 ns
001: 64 ns to less than 128 ns
010: 128 ns to less than 256 ns
011: 256 ns to less than 512 ns
100: 512 ns to less than 1 µs
101: 1 µs to less than 2 µs
110: 2 µs-4 µs
111: More than 4 µs
11:10 RO
11b Core
Active State Link PM Support (ASLPMS):
L0s & L1 entry supported.
L0s & L1 entry supported.
9:4 RO 04h Core
Max Link Width (MLW):
Indicates the maximum number of lanes
supported for this links.
Indicates the maximum number of lanes
supported for this links.
3:0 RO 1h Core
Max Link Speed (MLS):