Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
97
Bit Access Default
Value
RST/
PWR
Description
Hardwired to indicate 2.5 Gb/s.
1.7.19
DMILCTL - DMI Link Control
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
88-89h
Default Value:
0000h
Access:
RO; RW;
Size: 16
bits
Allows control of DMI.
Bit Acces
s
Defau
lt
Value
RST/
PWR
Description
15:8 RO 00h Core
Reserved ()
7 RW 0b
Core
Extended Synch (EXTSYNC):
0: Standard Fast Training Sequence (FTS). 1:
0: Standard Fast Training Sequence (FTS). 1:
Forces the transmission of additional ordered sets
when exiting the L0s state and when in the Recovery
state. This mode provides external devices
when exiting the L0s state and when in the Recovery
state. This mode provides external devices
(e.g., logic analyzers) monitoring the Link time to
achieve bit and symbol lock before the link enters L0
and resumes communication. This is a test
achieve bit and symbol lock before the link enters L0
and resumes communication. This is a test
mode only and may cause other undesired side
effects such as buffer overflows or under-runs.
effects such as buffer overflows or under-runs.
6:3 RO 0h Core
Reserved ()
2 RO 0b
Core
Reserved ()
1:0 RW 00b Core
Active State Power Management Support
(ASPMS):
Controls the level of active state power management
supported on the given link.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Supported
11: L0s and L1 Entry Supported
(ASPMS):
Controls the level of active state power management
supported on the given link.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Supported
11: L0s and L1 Entry Supported