Intel L7555 AT80604004875AA User Manual

32

Intel® Xeon® Processor 7500 Datasheet, Volume 1

Specifications for link speed independent specifications are called out in 

.

UIavg

Average UI size at “G” GT/

s (Where G = 4.8, 6.4, 

and so on)

0.999 * 

nominal

1000/G

1.001 * 

nominal

psec

T

rise-fall-pin-20-80

+/- 100mV@crossing

25 psec

0.25 UI

ΔZ

TX_LOW_CM_DC

Defined as:

(max(Z

TX_LOW_CM_DC

) - 

min(Z

TX_LOW_CM_DC

))

 

/

Z

TX_LOW_CM_DC 

expressed 

in %, over full range of Tx 

single ended voltage

-6

6

% of 

Z

TX_LOW_CM_DC

ΔZ

RX_LOW_CM_DC

Defined as:

(max(Z

TX_LOW_CM_DC

) - 

min(Z

TX_LOW_CM_DC

))

 

/

Z

TX_LOW_CM_DC 

expressed 

in %, over full range of Tx 

single ended voltage

-6

0

6

% of 

Z

TX_LOW_CM_DC

RL

RX

Return Loss of Receiver
Package measured at any 

data or clock signal inputs

See note

1

N

MIN-UI-Validation

# of UI over which the 

eye mask voltage and 

timing spec needs to be 

validated

1,000,000

Z

RX_HIGH_CM_DC

Single ended DC 

impedance to GND for 

either D+ or D- of any 

data bit at Tx

40k

Ω

2

Z

TX_LINK_DETECT

Link Detection Resistor

500

2000

Ω

V

TX_LINK_DETECT

Link Detection Resistor 

Pull-up Voltage

1.5

V

V

DIFF_IDLE

Voltage difference 

between D+ and D- when 

lanes are either in 

Electrical Idle or 

V

TX_LINK_DETECT

0.1 * V

Rx-

diff-pp-pin

V

T

DATA_TERM_SKEW

Skew between first to last 

data termination meeting 

Z

RX_LOW_CM_DC

128

UI

T

INBAND_RESET_

SENSE

Time taken by inband 

reset detector to sense 

Inband Reset

1.5

μs

Tclk

_DET

Time taken by clock 

detector to observe clock 

stability

20K

UI

T

CLK_FREQ_DET

Time taken by clock 

frequency detector to 

decide slow vs. 

operational clock after 

stable clock

32

Reference Clock 

Cycles

T

Refclk-Tx-Variability

Phase variability between 

reference Clk (at Tx input) 

and Tx output.

500

psec

T

Refclk-Rx-Variability

Phase variability between 

reference Clk (at Rx 

input) and Rx output.

1000

psec