Intel L7555 AT80604004875AA User Manual
Product codes
AT80604004875AA
Electrical Specifications
34
Intel® Xeon® Processor 7500 Datasheet, Volume 1
Notes:
1.
The UI size is dependent upon the reference clock frequency
2.
1300mVpp swing is recommended when CPU to CPU or CPU to IOH length is within 2” of max trace length.
Note that default value is 1100mVpp.
3.
Measure AC CM noise at the TX and decimate to its spectral components. For all spectral components above
3.2GHz, apply the attenuation of the channel at the appropriate frequency. If the resultant AC CM at the
receiver is met after taking out the appropriate spectral component and it meets the RX AC CM spec then
we can allow the transmitter AC CM noise to pass.
4.
Measured with neighboring lines being quiet and the remaining lines toggling PRBS patterns.
5.
DC CM can be relaxed to 0.20 min and 0.30 max Vdiffp-p swing if RX has wide DC common mode range.
Table 2-12. Parameter Values for Intel® QPI Phy1 Channel at 1/4 RefClk Frequency
Symbol
Parameter
Min
Nom
Max
Unit
Notes
V
Tx-diff-pp-pin
Transmitter differential swing
800
1500
mV
1
Z
TX_LOW_CM_DC
DC resistance of Tx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
pin
) bias point
38
47
Ω
Z
RX_LOW_CM_DC
DC resistance of Rx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
pin
) bias point
38
47
Ω
V
Tx-cm-dc-pin
Transmitter output DC common
mode, defined as average of V
D+
and V
D-
0.23
0.27
Fraction of
V
Tx-diff-pp-pin
5
V
Tx-cm-ac-pin
Transmitter output AC common
mode, defined as ((V
D+
+ V
D-
)/2 -
V
Tx-cm-dc-pin
)
-
0.0375
0.0375
Fraction of
V
Tx-diff-pp-pin
2
TX
duty-pin
Average of absolute UI-UI jitter
-0.002
0.0025
UI
1
TX
jitUI-UI-1E-7-pin
Absolute value of UI-UI jitter
measured at Tx output pins with
1E-7 probability.
-0.007
0.0075
UI
3
V
Rx-diff-pp-pin
Voltage eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
150
V
Tx-diff-pp-pin
mV
T
Rx-diff-pp-pin
Timing eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
0.9
1
UI
T
Rx-data-clk-skew-pin
Delay of any data lane relative to
the clock lane, as measured at the
end of Tx+ channel. This
parameter is a collective sum of
effects of data clock mismatches
in Tx and on the medium
connecting Tx and Rx.
-1
4
UI
VRx-CLK
Forward CLK Rx input voltage
sensitivity (differential pp)
150
mV
V
Rx-cm-dc-pin
DC common mode ranges at the
Rx input for any data or clock
channel
75
400
mV
V
Rx-cm-ac-pin
AC common mode ranges at the
Rx input for any data or clock
channel, defined as:
((V
((V
D+
+ V
D-
/2 - V
RX-cm-dc-pin
)
-50
50
mV
2