Intel 2 Duo T7200 LE80537GF0414M User Manual
Product codes
LE80537GF0414M
Errata
Specification Update
89
AH120
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error
Reporting Enable Correctly
Problem:
IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate
whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the
last update to the IA32_MC1_STATUS MSR. Due to this erratum, IA32_MC1_STATUS
MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit.
whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the
last update to the IA32_MC1_STATUS MSR. Due to this erratum, IA32_MC1_STATUS
MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit.
Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in
the IA32_MC1_CTL MSR at the time of the last update.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Table of Changes.
AH121
Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
Problem:
During the transition from real mode to protected mode, if an SMI (System
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from
System Management Mode) may cause the lower two bits of CS segment register to
be corrupted.
Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection
Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from
System Management Mode) may cause the lower two bits of CS segment register to
be corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no impact
unless software explicitly examines the CS segment register between enabling
protected mode and the first far JMP. Intel
protected mode and the first far JMP. Intel
®
64 and IA-32 Architectures Software
Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section
titled "Switching to Protected Mode" recommends the far JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially available software.
titled "Switching to Protected Mode" recommends the far JMP immediately follows the
write to CR0 to enable protected mode. Intel has not observed this erratum with any
commercially available software.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Table of Changes.
AH122
FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
Problem:
The FP (Floating Point) Data Operand Pointer is the effective address of the operand
associated with the last non-control FP instruction executed by the processor. If an
80-bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the
memory access wraps a 4-Gbyte boundary and the FP environment is subsequently
saved, the value contained in the FP Data Operand Pointer may be incorrect.
associated with the last non-control FP instruction executed by the processor. If an
80-bit FP access (load or store) uses a 32-bit address size in 64-bit mode and the
memory access wraps a 4-Gbyte boundary and the FP environment is subsequently
saved, the value contained in the FP Data Operand Pointer may be incorrect.
Implication: Due to this erratum, the FP Data Operand Pointer may be incorrect. Wrapping an 80-
bit FP load around a 4-Gbyte boundary in this way is not a normal programming
practice. Intel has not observed this erratum with any commercially available
software.
practice. Intel has not observed this erratum with any commercially available
software.
Workaround: If the FP Data Operand Pointer is used in a 64-bit operating system which may run
code accessing 32-bit addresses, care must be taken to ensure that no 80-bit FP
accesses are wrapped around a 4-Gbyte boundary.
accesses are wrapped around a 4-Gbyte boundary.