Intel 2 Duo T7200 LE80537GF0414M User Manual
Product codes
LE80537GF0414M
Errata
Specification Update
91
Erratum Affecting Only Intel
®
Core™2 Duo Mobile
Processors on Mobile Intel
®
965 Express Chipset Family
AH1P.
VM Exit Due to Virtual APIC-Access May Clear RF
Problem:
RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart instruction
execution without getting an instruction breakpoint on the instruction following a
debug breakpoint exception. Due to this erratum, in a system supporting Intel
execution without getting an instruction breakpoint on the instruction following a
debug breakpoint exception. Due to this erratum, in a system supporting Intel
®
Virtualization Technology, when a VM Exit occurs due to Virtual APIC-Access
(Advanced Programmable Interrupt Controller-Access) the EFLAGS/RFLAGS saved in
the VMCS (Virtual-Machine Control Structure) may contain an RF value of 0.
(Advanced Programmable Interrupt Controller-Access) the EFLAGS/RFLAGS saved in
the VMCS (Virtual-Machine Control Structure) may contain an RF value of 0.
Implication: When this erratum occurs, following a VM Exit due to a Virtual APIC-access, the
processor may unintentionally break on the subsequent instruction after VM entry.
Workaround: None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AH2P.
VMCALL Failure Due to Corrupt MSEG Location May Cause VM Exit to
Load the Machine State Incorrectly
Problem:
In systems supporting Intel Virtualization Technology, if a VMCALL failure occurs due
to a corrupt Monitor Segment (MSEG), subsequent VM Exits may load machine state
incorrectly.
to a corrupt Monitor Segment (MSEG), subsequent VM Exits may load machine state
incorrectly.
Implication: Occurrence of this erratum may result in a VMX abort.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AH3P.
Fixed Function Performance Counters MSR_PERF_FIXED_CTR1(30AH)
and MSR_PERF_FIXED_CTR2(30BH) are Note Cleared When the
Processor Is Reset
Problem:
The Fixed Function Performance Counters that count the number of core cycles and
reference cycles when the core is not in a halt state are not cleared when the
processor is reset.
reference cycles when the core is not in a halt state are not cleared when the
processor is reset.
Implication: The MSR_PERF_FIXED_CTR1 and MSR_PERF_FIXED_CTR2 counters may contain
unexpected values after reset.
Workaround: BIOS can workaround this erratum by clearing the counters at processor initialization
time.
Status:
For the steppings affected, see the Summary Tables of Changes.