Intel Xeon L3406 CM80616005010AA User Manual

Product codes
CM80616005010AA
Page of 302
Datasheet, Volume 2
173
Processor Integrated I/O (IIO) Configuration Registers
3.6.1.21
TXT.CMD.OPEN.LOCALITY1—Intel
®
 TXT Open Locality 1 
Command
Enables Locality 1 decoding in chipset.
General Behavioral Rules:
• This is a write-only register.
• This register is only available in the private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific 
meaning.
3.6.1.22
TXT.CMD.CLOSE.LOCALITY1—Intel
®
 TXT Close Locality 1 
Command
Disables Locality 1 decoding in chipset.
General Behavioral Rules:
• This is a write-only register.
• This register is only available in the private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific 
meaning.
3.6.1.23
TXT.CMD.OPEN.LOCALITY2—Intel
®
 TXT Open Locality 2 
Command
Enables Locality 2 decoding in chipset. This command will open Locality2 for decode as 
an Intel TXT space by the chipset. This command is either an TXTMW or a private write 
when private is open. 
Note:
OPEN.PRIVATE will open Locality 2 and CLOSE.PRIVATE will close Locality 2 without 
requiring an explicit OPEN/CLOSE.CMD.LOCALITY3 cycle.
The OPEN/CLOSE Locality 2 commands are to be used in the window while PRIVATE is 
open, but the VMM wants to close or re-open the Locality 2 space while still leaving 
PRIVATE open. 
If the locality is closed, then cycles to the Locality 2 address range are not decoded as 
Intel TXT cycles. 
Base: TXT_TXT Offset: 0380h
Bit
Attr
Default
Description
7:0
WO
0h
N/A
Base: TXT_TXT Offset: 0388h
Base: TXT_PR Offset: 0388h
Bit
Attr
Default
Description
7:0
WO
0h
N/A