Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
174
Datasheet, Volume 2
Note:
PRIVATE space must also be Open for Locality 2 to be decoded as Intel TXT space.
General Behavioral Rules:
• This is a write-only register.
• This register is only available in the private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
• This register is only available in the private Intel TXT configuration space.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
meaning.
3.6.1.24
TXT.CMD.CLOSE.LOCALITY2—Intel
®
TXT Close Locality 2
Command
Disables Locality 2 decoding in chipset. When closed, the chipset may decode this
range as normal memory space, or it may abort cycles to this range. This command is
either an TXTMW or a private write when private is open.
range as normal memory space, or it may abort cycles to this range. This command is
either an TXTMW or a private write when private is open.
General Behavioral Rules:
• This is a write-only register.
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
• Accesses to this register are done with 1-byte writes.
• The data bits associated with this command are undefined and have no specific
meaning.
3.6.1.25
TXT.PUBLIC.KEY—Intel
®
TXT Public Key Hash Register
Chipset public key hash.
Base: TXT_TXT Offset: 0390h
Base: TXT_PR Offset: 0390h
Bit
Attr
Default
Description
7:0
WO
0h
N/A
Base: TXT_TXT Offset: 0398h
Base: TXT_PROffset: 0398h
Bit
Attr
Default
Description
7:0
WO
0h
N/A
Base: TXT_TXT Offset: 0400h
Base: TXT_PR Offset: 0400h
Base: TXT_PBOffset: 0400h
Bit
Attr
Default
Description
256:0
RO
N/A