Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
205
Processor Uncore Configuration Registers
4.4.5
HDR—Header Type Register
This register identifies the header layout of the configuration space.
4.4.6
SVID—Subsystem Vendor Identification Register
This register identifies the manufacturer of the system. This 16-bit register combined
with the Device Identification Register uniquely identify any PCI device.
with the Device Identification Register uniquely identify any PCI device.
A write to any of the above registers on the processor will write to all of them.
Device:
0
Function: 0, 1
Offset:
08h
Device:
2
Function: 0, 1
Offset:
08h
Device:
3
Function: 0, 1, 4
Offset:
08h
Device:
4, 5
Function: 0–3
Offset:
08h
Bit
Attr
Default
Description
7
RO
1
Multi-Function Device
This bit selects whether this is a multi-function device, that may have
This bit selects whether this is a multi-function device, that may have
alternative configuration layouts. This bit is hardwired to 1 for devices in the
processor.
6:0
RO
0
Configuration Layout
This field identifies the format of the configuration header layout for a PCI-to-
This field identifies the format of the configuration header layout for a PCI-to-
PCI bridge from bytes 10h through 3Fh.
For all devices, the default is 00h, indicating a conventional type 00h PCI
For all devices, the default is 00h, indicating a conventional type 00h PCI
header.
Device:
0
Function: 0, 1
Offset:
2Ch
Device:
2
Function: 0, 1
Offset:
2Ch
Device:
3
Function: 0, 1, 4
Offset:
2Ch
Device:
4, 5
Function: 0–3
Offset:
2Ch
Bit
Attr
Default
Description
15:0
RWO
8086h
Vendor Identification Number
The default value specifies Intel.
The default value specifies Intel.