Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
207
Processor Uncore Configuration Registers
4.4.8
PCICMD—Command Register
This register defines the PCI 3.0 compatible command register values applicable to PCI
Express space.
Express space.
Device:
0
Function: 0, 1
Offset:
04h
Device:
2
Function: 0, 1
Offset:
04h
Device:
3
Function: 0, 1, 4
Offset:
04h
Device:
4, 5
Function: 0–3
Offset:
04h
Bit
Attr Default
Description
15:11
RV
0
Reserved. (by PCI-SIG)
10
RO
0
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages.
If this device does not generate interrupts, this bit is not implemented and is RO.
If this device generates interrupts, this bit is RW and this bit disables the
Controls the ability of the PCI Express port to generate INTx messages.
If this device does not generate interrupts, this bit is not implemented and is RO.
If this device generates interrupts, this bit is RW and this bit disables the
device/function from asserting INTx#. A value of 0 enables the assertion of its INTx#
signal. A value of 1 disables the assertion of its INTx# signal.
Legacy Interrupt mode is enabled
Legacy Interrupt mode is enabled
1 = Legacy Interrupt mode is disabled
9
RO
0
FB2B: Fast Back-to-Back Enable
This bit controls whether or not the master can do fast back-to-back writes. Since
This bit controls whether or not the master can do fast back-to-back writes. Since
this device is strictly a target this bit is not implemented. This bit is hardwired to 0.
Writes to this bit position have no effect.
8
RO
0
SERRE: SERR Message Enable
This bit is a global enable bit for this devices SERR messaging. This host bridge will
This bit is a global enable bit for this devices SERR messaging. This host bridge will
not implement SERR messaging. This bit is hardwired to 0. Writes to this bit position
have no effect.If SERR is used for error generation, then this bit must be RW and
enable/disable SERR signaling.
7
RO
0
IDSELWCC: IDSEL Stepping/Wait Cycle Control
Per the PCI 2.3 specification, this bit is hardwired to 0. Writes to this bit position have
Per the PCI 2.3 specification, this bit is hardwired to 0. Writes to this bit position have
no effect.
6
RO
0
PERRE: Parity Error Response Enable
Parity error is not implemented in this host bridge. This bit is hardwired to 0. Writes
Parity error is not implemented in this host bridge. This bit is hardwired to 0. Writes
to this bit position have no effect.
5
RO
0
VGAPSE: VGA palette snoop Enable
This host bridge does not implement this bit. This bit is hardwired to a 0. Writes to
This host bridge does not implement this bit. This bit is hardwired to a 0. Writes to
this bit position have no effect.
4
RO
0
MWIEN: Memory Write and Invalidate Enable
This host bridge will never issue memory write and invalidate commands. This bit is
This host bridge will never issue memory write and invalidate commands. This bit is
therefore hardwired to 0. Writers to this bit position will have no effect.
3
RO
0
SCE: Special Cycle Enable
This host bridge does not implement this bit. This bit is hardwired to a 0. Writers to
This host bridge does not implement this bit. This bit is hardwired to a 0. Writers to
this bit position will have no effect.
2
RO
1
BME: Bus Master Enable
This host bridge is always enabled as a master. This bit is hardwired to a 1. Writes to
This host bridge is always enabled as a master. This bit is hardwired to a 1. Writes to
this bit position have no effect.
1
RO
1
MSE: Memory Space Enable
This host bridge always allows access to main memory. This bit is not implemented
This host bridge always allows access to main memory. This bit is not implemented
and is hardwired to 1. Writes to this bit position have no effect.
0
RO
0
IOAE: Access Enable
This bit is not implemented in this host bridge and is hardwired to 0. Writes to this bit
This bit is not implemented in this host bridge and is hardwired to 0. Writes to this bit
position have no effect.