Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
237
Processor Uncore Configuration Registers
4.9.12
MC_TEST_EP_SCCTL
Memory test electrical parameter scan chain control register.
4.9.13
MC_TEST_EP_SCD
Memory test electrical parameter scan chain data register.
Device:
3
Function:
4
Offset:
F8h
Access as a DWord
Bit
Attr
Default
Description
31
RW1S
0
SCAN_READ
Perform a scan chain read.
Perform a scan chain read.
30
RW1S
0
SCAN_WRITE
Perform a san chain write.
Perform a san chain write.
29:16
RO
0
Reserved
15:0
RW
0
SCAN_OFFSET
Shift count to perform upon next shift command.
Shift count to perform upon next shift command.
Device:
3
Function:
4
Offset:
FCh
Access as a DWord
Bit
Attr
Default
Description
31:0
RW
0
DATA
Contains the data written to or read from the scan chain.
Contains the data written to or read from the scan chain.