Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
239
Processor Uncore Configuration Registers
4.10.2
MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD
Integrated Memory Controller DIMM initialization command register. This register is
used to sequence the channel through the physical layer training required for DDR.
used to sequence the channel through the physical layer training required for DDR.
Device:
4, 5
Function:
0
Offset:
54h
Access as a DWord
Bit
Attr
Default
Description
31:18
RO
0
Reserved
17
WO
0
ASSERT_CKE
When set, all CKE will be asserted. Write a 0 to this bit to stop the init
When set, all CKE will be asserted. Write a 0 to this bit to stop the init
block from driving CKE. This bit has no effect once INIT_DONE is set.
16
RW
0
DO_RCOMP
When set, an RCOMP will be issued to the rank specified in the RANK field.
When set, an RCOMP will be issued to the rank specified in the RANK field.
15
RW
0
DO_ZQCL
When set, a ZQCL will be issued to the rank specified in the RANK field.
When set, a ZQCL will be issued to the rank specified in the RANK field.
14
RW
0
WRDQDQS_MASK
When set, the Write DQ-DQS training will be skipped.
When set, the Write DQ-DQS training will be skipped.
13
RW
0
WRLEVEL_MASK
When set, the Write Levelization step will be skipped.
When set, the Write Levelization step will be skipped.
12
RW
0
RDDQDQS_MASK
When set, the Read DQ-DQS step will be skipped.
When set, the Read DQ-DQS step will be skipped.
11
RW
0
RCVEN_MASK
When set, the RCVEN step will be skipped.
When set, the RCVEN step will be skipped.
10
WO
0
RESET_FIFOS
When set, the TX and RX FIFO pointers will be reset at the next BCLK
When set, the TX and RX FIFO pointers will be reset at the next BCLK
edge. The Bubble Generators will also be reset.
9
RW
0
IGNORE_RX
When set, the read return datapath will ignore all data coming from the RX
When set, the read return datapath will ignore all data coming from the RX
FIFOS. This is done by gating the early valid bit.
8
RW
0
STOP_ON_FAIL
When set along with the AUTORESETDIS not being set, the phyinit FSM will
When set along with the AUTORESETDIS not being set, the phyinit FSM will
stop if a step has not completed after timing out.
7:5
RW
0
RANK
The rank currently being tested. The PhyInit FSM must be sequenced for
The rank currently being tested. The PhyInit FSM must be sequenced for
every rank present in the channel. The rank value is set to the rank being
trained.
4:2
RW
0
NXT_PHYINIT_STATE
Set to sequence the physical layer state machine.
000 = IDLE
001 = RD DQ-DQS
010 = RcvEn Bitlock
011 = Write Level
100 = WR DQ-DQS.
Set to sequence the physical layer state machine.
000 = IDLE
001 = RD DQ-DQS
010 = RcvEn Bitlock
011 = Write Level
100 = WR DQ-DQS.
1
RW
0
AUTODIS
Disables the automatic training where each step is automatically
Disables the automatic training where each step is automatically
incremented. When set, the physical layer state machine must be
sequenced with software. The training FSM must be sequenced using the
NXT_PHYINIT_STATE field.
0
WO
0
TRAIN
Cycle through the training sequence for the rank specified in the RANK
Cycle through the training sequence for the rank specified in the RANK
field.