Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
255
Processor Uncore Configuration Registers
4.10.23 MC_CHANNEL_0_WAQ_PARAMS
MC_CHANNEL_1_WAQ_PARAMS
This register contains parameters that specify settings for the Write Address Queue.
Device:
4, 5
Function:
0
Offset:
B4h
Access as a DWord
Bit
Attr
Default
Description
31:30
RO
0
Reserved
29:25
RW
6
PRECASWRTHRESHOLD
Threshold above which Medium-Low Priority reads cannot PRE-CAS write
Threshold above which Medium-Low Priority reads cannot PRE-CAS write
requests.
24:20
RW
31
PARTWRTHRESHOLD
Threshold used to raise the priority of underfill requests in the scheduler.
Threshold used to raise the priority of underfill requests in the scheduler.
Set to 31 to disable.
19:15
RW
31
ISOCEXITTHRESHOLD
Write Major Mode ISOC Exit Threshold. When the number of writes in the
Write Major Mode ISOC Exit Threshold. When the number of writes in the
WAQ drops below this threshold, the MC will exit write major mode in the
presence of a read.
14:10
RW
31
ISOCENTRYTHRESHOLD
Write Major Mode ISOC Entry Threshold. When the number of writes in the
Write Major Mode ISOC Entry Threshold. When the number of writes in the
WAQ exceeds this threshold, the MC will enter write major mode in the
presence of a read.
9:5
RW
22
WMENTRYTHRESHOLD
Write Major Mode Entry Threshold. When the number of writes in the WAQ
Write Major Mode Entry Threshold. When the number of writes in the WAQ
exceeds this threshold, the MC will enter write major mode.
4:0
RW
22
WMEXITTHRESHOLD
Write Major Mode Exit Threshold. When the number of writes in the WAQ
Write Major Mode Exit Threshold. When the number of writes in the WAQ
drop below this threshold, the MC will exit write major mode.