Intel Xeon L3406 CM80616005010AA User Manual

Datasheet, Volume 2

257

These are the parameters used to set the Start Scheduler for TX clock crossing. This is 
used to send commands to the DIMMs.

The NATIVE RATIO is UCLK multiplier of BCLK = U

ALIEN RATIO is DCLK multiplier of BCLK = D

PIPE DEPTH = 8 UCLK (design dependent variable)

MIN SEP DELAY = 670 ps (design dependent variable, Internally this is logic delay of 
FIFO + clock skew between U and D)

TOTAL EFFECTIVE DELAY = PIPE DEPTH * UCLK PERIOD in ps + MIN SEP DELAY

DELAY FRACTION = (TOTAL EFFECTIVE DELAY * D) / (UCLK PERIOD in ps * G.C.D(U,D)

Determine OFFSET MULTIPLE using the equation 

FLOOR ((OFFSET MULTIPLE +1) / G.C.D (U,D)) > DELAY FRACTION

OFFSET VALUE = MOD (OFFSET MULTIPLE, U) ≤ Final answer for OFFSET MULTIPLE

31:17

RO

0

23:16

RW

2

OFFSET
TX offset setting.

15:8

RW

1

ALIENRATIO
Dclk ratio to BCLK. TX Alien Ratio setting.

7:0

RW

4

NATIVERATIO
Uclk ratio to BCLK. TX Native Ratio setting.