Intel Xeon L3406 CM80616005010AA User Manual

Datasheet, Volume 2

299

1.

Note that VTBAR range would be within the MMIOL range of that IIO. And by that token, VTBAR range can 

never overlap with any DRAM ranges.

2.

The CB DMA BAR and I/OxAPIC MBAR regions of an IIO overlap with MMIOL/MMIOH ranges of that IIO.

3.

CB DMA does not support generating memory accesses to the VGA memory range and it will abort all 

transactions to that address range. Also, if peer-to-peer memory read disable bit is set, VGA memory reads 

are aborted.

4.

If peer-to-peer memory read disable bit is set, then peer-to-peer memory reads are aborted.

Other Peer-to-Peer

4

Address within LMMIOL.BASE/LMMIOL.LIMIT 

or LMMIOH.BASE/LMMIOH.LIMIT and a PCIe 

port positively decoded as target

Forward to the PCI Express port

Address within LMMIOL.BASE/LMMIOL.LIMIT 

or LMMIOH.BASE/LMMIOH.LIMIT and no PCIe 

port positively decoded as target

Forward to DMI

Address NOT within 

LMMIOL.BASE/LMMIOL.LIMIT or 

LMMIOH.BASE/LIOH.LIMIT, but is within 

GMMIOL.BASE/GMMIOL.LIMIT or 

GMMIOH.BASE/GMMIOH.LIMIT

Forward to Intel QuickPath 

Interconnect
For the processor, this is not 

applicable as GMMIOH and LMMIOH 

must be programmed to the same 

values.

DRAM Memory holes 

and other non-existent 

regions

• {4G ≤ Address ≤ TOHM (OR) 0 ≤ Address ≤ 

TOLM} AND address does not decode to 

any socket in Intel QuickPath 

Interconnect source decoder

• Address  >  TOCM
• When Intel VT-d translation enabled, and 

guest address greater than 2^GPA_LIMIT

Master Abort

All Else

Forward to subtractive decode port.