Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
79
Processor Integrated I/O (IIO) Configuration Registers
3.3.5
PCIe/DMI Extended Configuration Space
This section describes the extended configuration space (100h to 1FCh) for PCI Express
and DMI ports.
and DMI ports.
3.3.5.1
APICBASE—APIC Base Register
3.3.5.2
APICLIMIT—APIC Limit Register
3.3.5.3
PERFCTRLSTS—Performance Control and Status Register
Register:
APICBASE
Device:
0 (DMI), 3-6 (PCIe)
Function:
0
Offset:
140h
Bit
Attr
Default
Description
15:12
RO
0h
Reserved
11:1
RW
0h
Bits 19:9 of the APIC Base
Bits 31:20 are assumed to be FECh. Bits 8:0 are don’t care for address
Bits 31:20 are assumed to be FECh. Bits 8:0 are don’t care for address
decode. Address decoding to the APIC range is done as APIC_BASE[31:8] ≤
A[31:8] ≤ APIC_LIMIT[31:8].
0
RW
0h
APIC Range Enable
Enables the decode of the APIC window.
Enables the decode of the APIC window.
Register:
APICLIMIT
Device:
0 (DMI), 3-6 (PCIe)
Function:
0
Offset:
142h
Bit
Attr
Default
Description
15:12
RO
0h
Reserved
11:1
RW
0h
Bits 19:9 of the APIC Limit
Bits 31:20 are assumed to be FECh. Bits 8:0 are a don’t care for address
Bits 31:20 are assumed to be FECh. Bits 8:0 are a don’t care for address
decode. Address decoding to the APIC range is done as APIC_BASE[31:8] ≤
A[31:8] ≤ APIC_LIMIT[31:8].
0
RO
0h
Reserved
(Sheet 1 of 2)
Register:
PERFCTRLSTS
Device:
0 (DMI), 3-6 (PCIe)
Function:
0
Offset:
180h
Bit
Attr
Default
Description
63:42
RO
0
Reserved
41
RO
0
Reserved
40
RV
0
Reserved
39:36
RO
0
Reserved
35
RV
0
Reserved
34:21
RV
0
Reserved