Intel Xeon L3406 CM80616005010AA User Manual

80

Datasheet, Volume 2

20:16

RW

18h

Number of Outstanding RFOs/Pre-Allocated Non-Posted Requests for PCI 

Express Gen1
This register controls the number of outstanding inbound non-posted 

requests - I/O, config, memory - that a Gen1 PCI Express downstream port 

can have, for all non-posted requests (peer-to-peer or to main-memory) it 

pre-allocates buffer space for. The value of this parameter for the port when 

operating in Gen1 x8 width is obtained by multiplying this register by 2 and 

4, respectively. Software programs this register based on the read/RFO 

latency to main memory. 
A value of 1 indicates one outstanding pre-allocated request, 2 indicates 2 

outstanding pre-allocated requests and so on. If software programs a value 

greater than the buffer size the DMA engine supports, then the maximum 

hardware supported value is used.

15:14

RO

0

Reserved

13:8

RW

30h

Number of Outstanding Pre-Allocated Non-Posted Requests for PCI Express 

Gen2
This register controls the number of outstanding inbound non-posted 

requests - I/O, config, memory - (maximum length of these requests is a 

CL) that a Gen1 PCI Express downstream port can have, for all non-posted 

requests (peer-to-peer or to main-memory) it pre-allocates buffer space for. 

The value of this parameter for the port when operating in Gen2 width is 

obtained by multiplying this register by 2 and 4, respectively. Software 

programs this register based on the read/RFO latency to main memory.
A value of 1 indicates one outstanding pre-allocated request, 2 indicates 2 

outstanding pre-allocated requests and so on. If software programs a value 

greater than the buffer size the DMA engine supports, then the maximum 

hardware supported value is used.

7

RO

0

Reserved

6

RO

0

Reserved

5

RO

0

Reserved

4

RO

0

Reserved

3

RW

0

Enable No-Snoop Write Optimization on Writes
When set, inbound writes to memory with NS=1 will be treated as non-

coherent (no snoops) writes on Intel QuickPath Interconnect and pipelined 

to the processor node. 

1.

This bit should be set to the same value as Bit 2 (Enable No-Snoop 

Optimization on reads) of this register.

2.

This must be set for DMI port to support Isoch traffic. For PCI Express 

ports the NS optimization must not be used and this bit should be zero.

2

RW

0

Enable No-Snoop Optimization on Reads
When set, memory reads with NS=1 will not be snooped on Intel QuickPath 

Interconnect.

1.

This bit should be set to the same value as Bit 3 (Enable No-Snoop 

Optimization on writes) of this register.

2.

This must be set for DMI port to support Isoch traffic. For PCI Express 

ports the NS optimization must not be used and this bit should be zero.

1

RO

0

Reserved 

0

RO

0

Reserved