Intel Itanium 9330 LW80603004728AA User Manual

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FLASHROM_CFG[2:0]

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These are input signals to the processor that would initialize and map the Flash 

ROM upon reset. After reset is deasserted this input would be ignored by the 

processor logic. These pins are sampled during all resets except warm-logic reset.

FLASHROM_CLK

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The Flash ROM clock.

FLASHROM_CS[3:0]_N

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Flash ROM chip selects. Up to four separate flash ROM parts may be used.

FLASHROM_DATI

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Serial Data Input (from ROM(s) to processor). 

FLASHROM_DATO

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Serial Data Output (from processor to ROM(s))

FLASHROM_WP_N

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Flash ROM write-protect.

FORCEPR_N

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When logic 0, forces processor power reduction through the FOXTON controller.
Refer to Intel® Itanium® 9300 Series External Design Specification for detailed 

signal description.

LRGSCLSYS

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The header mode is selected by the LRGSCLSYS strapping pin value sampled only 

during COLD reset. LRGSCLSYS, when tied to 1.1 V using a 50 ohm resistor, puts 

the processor in extended header mode, and LRGSCLSYS, when tied to GND, puts 

the the processor in standard header mode.

MEM_THROTTLE_L

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When this pin is asserted, the internal memory controllers throttle the memory 

command issue rate to a configurable fraction of the nominal command rate 

settings.

PIR_SCL

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(Processor Information ROM Serial Clock): The PIR_SCL input clock is used to clock 

data into and out of the on package PIROM device. This signal applies to the 

EEPROM, which is composed of the PIROM and the OEM Scratch PAD.

PIR_SDA

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(Processor Information ROM Serial Data): The PIR_SDA pin is a bidirectional signal 

for serial data transfer. This signal applies to the EEPROM, which is composed of the 

PIROM and the OEM Scratch PAD

PIR_A0, PIR_A1

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(Processor Information ROM Address[0:1]): The PIR_A[0:1] pins are used as the 

PIROM memory address selection signals. This bus applies to the EEPROM, which is 

composed of the PIROM and the OEM Scratch PAD

SM_WP

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WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch 

EEPROM is write-protected when this input is pulled high to VCC33_SM. 

PRBMODE_REQ_N

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Input from Extended Debug Port (XDP) to make a probe mode request.

PRBMODE_RDY_N

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Output to XDP to acknowledge probe mode request.

PROCHOT_N

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The assertion of PROCHOT_N (processor hot) indicates that the processor die 

temperature has reached its thermal limit. 

PROCTYPE

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PROCTYPE output informs the platform the processor type. PROCTYPE is tied to VSS 

internally to indicate the Intel® Itanium® processor 9300 series. This pin does not 

require a platfrom pull-up or pull-down.

PWRGOOD

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The processor requires this signal to be a clean indication that all the processor 

clocks and power supplies are stable and within their specifications. “Clean” implies 

that the signal will remain low (capable of sinking leakage current), without 

glitches, from the time that the power supplies are turned on until they come within 

specification. The signal must then transition monotonically to a high state. 

PWRGOOD can be driven inactive at any time, but clocks and power must again be 

stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to 

protect internal circuits against voltage sequencing issues. It should be driven high 

throughout boundary scan operation. 

RESET_N

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Asserting the RESET_N signal resets the processor to a known state and invalidates 

its internal caches without writing back any of their contents. BOOTMODE[0:1] 

signals are sampled during all RESET_N assertions for selecting appropriate 

BOOTMODE. 

RSVD

These pins are reserved and should be left unconnected. 

SKTID[2:0]

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Socket ID strapping pins.

 

To pull any of these inputs high, they should be strapped 

to VCCIO, and to pull them low, they should be strapped to VSS. SKTID[2:0] 

partially determine the node address.