Kingston Technology KHX6400D2B1/1G Data Sheet
Memory Module Specifications
KHX6400D2B1/1G
1GB 128M x 64-Bit PC2-6400
CL5 240-Pin DIMM
CL5 240-Pin DIMM
Kingston.com
Document No. 4805597-001.B00 07/18/11 Page 1
DESCRIPTION
This document describes Kingston’s 128M x 64-bit 1GB
(1024MB) DDR2-800 CL5 SDRAM (Synchronous DRAM)
memory module, based on eight 128M x 8-bit DDR2 FBGA
components. The SPD is programmed to JEDEC standard
latency 800MHz timing of 5-5-5-15 at 1.8V. This 240-pin
DIMM uses gold contact fingers and requires +1.8V. The
electrical and mechanical specificationsare as follows:
(1024MB) DDR2-800 CL5 SDRAM (Synchronous DRAM)
memory module, based on eight 128M x 8-bit DDR2 FBGA
components. The SPD is programmed to JEDEC standard
latency 800MHz timing of 5-5-5-15 at 1.8V. This 240-pin
DIMM uses gold contact fingers and requires +1.8V. The
electrical and mechanical specificationsare as follows:
SPECIFICATIONS
Clock Cycle Time (tCK) CL=5
2.5ns (min.) / 8ns (max.)
Row Cycle Time (tRC)
57.5ns (min.)
Refresh to Active/Refresh
127.5ns
Command Time (tRFC)
Row Active Time (tRAS)
45ns (min.) / 70,000ns (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power
1.040 W (operating)
UL Rating
94 V - 0
Operating Temperature
0° C to 55° C
Storage Temperature
-55° C to +125° C
FEATURES
• Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
• Double-data-rate architecture; two data transfers per
• Double-data-rate architecture; two data transfers per
clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 5 (clock)
• Burst Length: 4, 8 (Interleave/nibble sequential)
• Programmable Burst type (sequential & interleave)
• Timing Reference: 800MHz 5-5-5-15 at +1.8V
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
• Serial presence detect with EEPROM
• High Performance Heat Spreader
• PCB : Height 1.180” (30.00mm), single sided component
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 5 (clock)
• Burst Length: 4, 8 (Interleave/nibble sequential)
• Programmable Burst type (sequential & interleave)
• Timing Reference: 800MHz 5-5-5-15 at +1.8V
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
• Serial presence detect with EEPROM
• High Performance Heat Spreader
• PCB : Height 1.180” (30.00mm), single sided component
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