Intel QX9775 EU80574XL088N Data Sheet

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When the TM1 is enabled, and a high temperature situation exists (that is, TCC is 

active), the clocks will be modulated by alternately turning the clocks off and on at a 

duty cycle specific to the processor (typically 30 – 50%). Cycle times are processor 

speed dependent and will decrease as processor core frequencies increase. A small 

amount of hysteresis has been included to prevent rapid active/inactive transitions of 

the TCC when the processor temperature is near its maximum operating temperature. 

Once the temperature has dropped below the maximum operating temperature, and 

the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.

With thermal solutions designed to the processor Thermal Profile, it is anticipated that 

the TCC would only be activated for very short periods of time when running the most 

power intensive applications. The processor performance impact due to these brief 

periods of TCC activation is expected to be so minor that it would be immeasurable. 

Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see 

The duty cycle for the TCC, when activated by the TM1, is factory configured and 

cannot be modified. The TM1 does not require any additional hardware, software 

drivers, or interrupt handling routines.

The processor adds supports for an Enhanced Thermal Monitor capability known as 

Thermal Monitor 2 (TM2). This mechanism provides an efficient means for limiting the 

processor temperature by reducing the power consumption within the processor. TM2 

requires support for dynamic VID transitions in the platform.

When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the 

Thermal Control Circuit (TCC) will be activated for both processor cores. The TCC 

causes the processor to adjust its operating frequency (via the bus multiplier) and 

input voltage (via the VID signals). This combination of reduced frequency and VID 

results in a reduction to the processor power consumption.

A processor enabled for Thermal Monitor 2 includes two operating points, each 

consisting of a specific operating frequency and voltage, which is identical for both 

processor cores. The first operating point represents the normal operating condition for 

the processor. Under this condition, the core-frequency-to-system-bus multiplier used 

by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID that is 

The second operating point consists of both a lower operating frequency and voltage. 

The lowest operating frequency is determined by the lowest supported bus ratio (1/6 

for the processor. When the TCC is activated, the processor automatically transitions to 

the new frequency. This transition occurs rapidly, on the order of 5 µs. During the 

frequency transition, the processor is unable to service any bus requests, and 

consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and 

kept pending until the processor resumes operation at the new frequency.

Once the new operating frequency is engaged, the processor will transition to the new 

core operating voltage by issuing a new VID code to the voltage regulator. The voltage 

regulator must support dynamic VID steps in order to support Thermal Monitor 2. 

During the voltage change, it will be necessary to transition through multiple VID codes 

to reach the target operating voltage. Each step will be one VID table entry (see 

). The processor continues to execute instructions during the voltage 

transition. Operation at the lower voltage reduces the power consumption of the 

processor.

A small amount of hysteresis has been included to prevent rapid active/inactive 

transitions of the TCC when the processor temperature is near its maximum operating 

temperature. Once the temperature has dropped below the maximum operating 

temperature, and the hysteresis timer has expired, the operating frequency and