Intel QX9775 EU80574XL088N Data Sheet

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PROCHOT# is designed to assert at or a few degrees higher than maximum T

CASE

 when 

dissipating TDP power, and cannot be interpreted as an indication of processor case 

temperature. This temperature delta accounts for processor package, lifetime and 

manufacturing variations and attempts to ensure the Thermal Control Circuit is not 

activated below maximum T

CASE

 when dissipating TDP power. There is no defined or 

fixed correlation between the PROCHOT# trip temperature, or the case temperature. 

Thermal solutions must be designed to the processor specifications and cannot be 

adjusted based on experimental measurements of T

CASE

, or PROCHOT#.

The FORCEPR# (force power reduction) input can be used by the platform to cause the 

processor to activate the TCC. If the Thermal Monitor is enabled, the TCC will be 

activated upon the assertion of the FORCEPR# signal. Assertion of the FORCEPR# 

signal will activate TCC for all processor cores. The TCC will remain active until the 

system deasserts FORCEPR#. FORCEPR# is an asynchronous input. FORCEPR# can be 

used to thermally protect other system components. To use the VR as an example, 

when FORCEPR# is asserted, the TCC circuit in the processor will activate, reducing the 

current consumption of the processor and the corresponding temperature of the VR.

It should be noted that assertion of FORCEPR# does not automatically assert 

PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high 

temperature situation is detected. A minimum pulse width of 500 µs is recommended 

when FORCEPR# is asserted by the system. Sustained activation of the FORCEPR# 

signal may cause noticeable platform performance degradation.

Regardless of whether or not Thermal Monitor 1 or Thermal Monitor 2 is enabled, in the 

event of a catastrophic cooling failure, the processor will automatically shut down when 

the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in 

). At this point, the FSB signal THERMTRIP# will go active and stay active as 

. THERMTRIP# activation is independent of processor activity 

and does not generate any bus cycles. Intel also recommends the removal of V

TT

.

PECI offers an interface for thermal monitoring of Intel processor and chipset 

components. It uses a single wire, thus alleviating routing congestion issues. 

 shows an example of the PECI topology in a system with the Intel

®

 Core™2 

Extreme processor QX9775. PECI uses CRC checking on the host side to ensure reliable 

transfers between the host and client devices. Also, data transfer speeds across the 

PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI 

interface on the processor is disabled by default and must be enabled through BIOS.