Intel Core™2 Extreme Processor QX6800 (8M Cache, 2.93 GHz, 1066 MHz FSB) HH80562XH0778M Data Sheet

Product codes

HH80562XH0778M

Datasheet

Introduction

The Intel

Core™2 Extreme quad-core processor QX6800 is a desktop quad core

processor that combines the performance and power efficiencies of four low-power

microarchitecture cores to enable a new level of multi-tasking, multi-media, and

gaming experiences. The Intel

Core™2 Extreme quad-core processor QX6800 is a 64-

bit processor that maintains compatibility with IA-32 software.

The processor uses Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs

into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the

LGA775 socket.

Note:

In this document the Intel

Core™2 Extreme quad-core processor QX6800 will be

referred to simply as "the processor."

The processor is a quad core processor, based on 65 nm process technology, that uses

a 130 W thermal design power (TDP). The processor has a 1066 MHz front side bus

(FSB) and two independent but shared 4 MB of L2 cache (2x4M). The processor

supports all the existing Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD

Extensions 3 (SSE3). MNI are expected to improve multi-media performance as these

new instructions are enabled in applications. The processor supports several Advanced

Technologies: Execute Disable Bit, Intel

64, and Intel

Virtualization Technology (VT).

The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol

like the Intel

Pentium

4 processor. The FSB uses Source-Synchronous Transfer (SST)

of address and data to improve performance by transferring data four times per bus

clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address

bus can deliver addresses two times per bus clock and is referred to as a "double-

clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus

provide a data bus bandwidth of up to 8.5 GB/s.

Supported platforms may need to be refreshed to ensure the correct voltage regulation

(VRD11) and PECI support is enabled. Manufacturability is a high priority; hence,

mechanical assembly may be completed from the top of the baseboard and should not

require any special tooling.

The processor includes an address bus power-down capability that removes power from

the address and data signals when the FSB is not in use. This feature is always enabled

on the processor.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in

the active state when driven to a low level. For example, when RESET# is low, a reset

has been requested. Conversely, when NMI is high, a nonmaskable interrupt has

occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the ‘#’ symbol implies

that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front Side Bus” refers to the interface between the processor and system core logic

(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,

memory, and I/O.