Intel 2 Duo U7500 LE80537UE0042M User Manual
Product codes
LE80537UE0042M
Datasheet
79
Package Mechanical Specifications and Pin Information
SLP#
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts. The processor will
recognize only assertion of the RESET# signal, deassertion of
SLP#, and removal of the BCLK input while in Sleep state. If SLP#
is deasserted, the processor exits Sleep state and returns to Stop-
Grant state, restarting its internal clock signals to the bus and
processor core units. If DPSLP# is asserted while in the Sleep
state, the processor will exit the Sleep state and transition to the
Deep Sleep state.
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts. The processor will
recognize only assertion of the RESET# signal, deassertion of
SLP#, and removal of the BCLK input while in Sleep state. If SLP#
is deasserted, the processor exits Sleep state and returns to Stop-
Grant state, restarting its internal clock signals to the bus and
processor core units. If DPSLP# is asserted while in the Sleep
state, the processor will exit the Sleep state and transition to the
Deep Sleep state.
SMI#
Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt,
the processor saves the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM
handler.
If SMI# is asserted during the deassertion of RESET# the
processor will tristate its outputs.
by system logic. On accepting a System Management Interrupt,
the processor saves the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM
handler.
If SMI# is asserted during the deassertion of RESET# the
processor will tristate its outputs.
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
(also known as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
provides the serial input needed for JTAG specification support.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
TDO provides the serial output needed for JTAG specification
support.
TEST1,
TEST2, TEST3,
TEST4
TEST2, TEST3,
TEST4
Input
TEST1 and TEST2 must have a stuffing option of separate pull
down resistors to V
down resistors to V
SS
.
For testing purposes it is recommended, but not required, to route
the TEST3 and TEST4 pins through a ground referenced 55-Ω trace
that ends in a via that is near a GND via and is accessible through
an oscilloscope connection.
the TEST3 and TEST4 pins through a ground referenced 55-Ω trace
that ends in a via that is near a GND via and is accessible through
an oscilloscope connection.
THERMDA
Other
Thermal Diode Anode.
THERMDC
Other
Thermal Diode Cathode.
THERMTRIP#
Output
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125°C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125°C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
Table 16.
Signal Description (Sheet 7 of 8)
Name
Type
Description