Intel 2 Duo U7500 LE80537UE0042M User Manual

Datasheet

89

The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal 

Monitor control register is written to a 1, the TCC will be activated immediately 

independent of the processor temperature. When using on-demand mode to activate 

the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the 

same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is 

fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be 

programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. 

On-demand mode may be used at the same time automatic mode is enabled, however, 

if the system tries to enable the TCC via on-demand mode at the same time automatic 

mode is enabled and a high temperature condition exists, automatic mode will take 

precedence. 

An external signal, PROCHOT# (processor hot) is asserted when the processor detects 

that its temperature is above the thermal trip point. Bus snooping and interrupt 

latching are also active while the TCC is active. 

Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also 

includes one ACPI register, one performance counter register, three MSR, and one I/O 

pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal 

Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt 

upon the assertion or deassertion of PROCHOT#. 

PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep 

Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be 

used as a safeguard to maintain the processor junction temperature within maximum 

specification. If the platform thermal solution is not able to maintain the processor 

junction temperature within the maximum specification, the system must initiate an 

orderly shutdown to prevent damage. If the processor enters one of the above low 

power states with PROCHOT# already asserted, PROCHOT# will remain asserted until 

the processor exits the low power state and the processor junction temperature drops 

below the thermal trip point. 

If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out 

of specification. Regardless of enabling the automatic or on-demand modes, in the 

event of a catastrophic cooling failure, the processor will automatically shut down when 

the silicon has reached a temperature of approximately 125°C. At this point the 

THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor 

activity and does not generate any bus cycles. When THERMTRIP# is asserted, the 

processor core voltage must be shut down within the time specified in 

.

The processor also contains an on-die digital thermal sensor that can be read via a MSR 

(no I/O interface). In a dual-core implementation of the processor, each core will have 

a unique digital thermal sensor whose temperature is accessible via processor MSR. 

The digital thermal sensor is the preferred method of reading the processor die 

temperature since it can be located much closer to the hottest portions of the die and 

can thus more accurately track the die temperature and potential activation of 

processor core clock modulation via the Intel Thermal Monitor. The digital thermal 

sensor is only valid while the processor is in the normal operating state (C0 state).

Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature 

relative to the maximum supported operating temperature of the processor (T

J,max

). It 

is the responsibility of software to convert the relative temperature to an absolute 

temperature. The temperature returned by the digital thermal sensor will always be at 

or below T

J,max

. Over temperature conditions are detectable via an Out Of Spec status 

bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the 

processor is operating out of specification and immediate shutdown of the system 

should occur. The processor operation and code execution is not guaranteed once the 

activation of the Out of Spec status bit is set.