Intel E7520 AT80604004887AA User Manual

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Intel® Xeon® Processor 7500 Series Datasheet, Volume 1

measured with regards to the edges of a separate clock signal at any other point. 
Each differential signal pair by combining the D+ and D- signals produces a signal 
eye. A _DN and _DP after a signal name refers to a differential pair.

• FC-LGA-1567 — The Intel

®

 Xeon

® 

processor 7500 series is available in a Flip-Chip 

Land Grid Array (FC-LGA) package, consisting of 8 processor cores mounted on a 
pinned substrate with an integrated heat spreader (IHS).

• Functional Operation — Refers to the normal operating conditions in which all 

processor specifications, including DC, AC, system bus, signal quality, mechanical, 
and thermal, are satisfied.

• Integrated Heat Spreader (IHS) — A component of the processor package used 

to enhance the thermal performance of the package. Component thermal solutions 
interface with the processor at the IHS surface.

• Intel® QuickPath Interconnect (Intel® QPI) — Previously referred to as 

Common System Interface (CSI), Intel

®

 QuickPath Interconnect is a cache-

coherent, links-based interconnect specification for Intel processor, chipset, and I/
O bridge components.

• Intel® Scalable Memory Interconnect (Intel® SMI) - Previously referred to 

as FBD2 or fully buffered DIMM 2 interface, Intel

®

 Scalable Memory Interconnect is 

a bridge to the Intel

®

 7500 Scalable Memory Buffer.

• Intel® Turbo Boost Technology — Intel Turbo Boost Technology is a way to 

automatically run the processor core faster than the marked frequency if the part is 
operating under power, temperature, and current specifications limits of the 
Thermal Design Power (TDP). This results in increased performance of both single 
and multi-threaded applications.

• Intel® Xeon® Processor 7500 Series — The entire product, including processor 

core, die, substrate and integrated heat spreader (IHS).

• Jitter — Any timing variation of a transition edge or edges from the defined UI.
• MP — Multi-processor system consisting of more than two processors.
• OEM — Original Equipment Manufacturer.
• Processor Information ROM (PIROM) — A memory device located on the 

processor and accessible via the System Management Bus (SMBus) which contains 
information regarding the processor’s features. This device is shared with the 
Scratch EEPROM, is programmed during manufacturing, and is write-protected.

• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) 

— A memory device located on the processor and addressable via the SMBus which 
can be used by the OEM to store information useful for system management.

• SMBus — System Management Bus. A two-wire interface through which simple 

system and power management related devices can communicate with the rest of 
the system. It is based on the principals of the operation of the I

2

C two-wire serial 

bus developed by Phillips Semiconductor. SMBus is a subset of the I

2

C bus/protocol 

developed by Intel. Implementations of the I

2

C bus/protocol or the SMBus bus/

protocol may require licensing from various entities, including, but not restricted to, 
Philips Electronics N.V. and North American Philips Corporation.

• Storage Conditions — Refers to a non-operational state. The processor may be 

installed in a platform, in a tray, or loose. Processors may be sealed in packaging or 
exposed to free air. Under these conditions, processor pins should not be connected 
to any supply voltages, have any I/Os biased, or receive any clocks.

• Unit Interval (UI) — Intel

®

 QPI signaling convention is binary and unidirectional. 

In this binary signaling, one bit is sent for every edge of the forwarded clock,