Intel E7520 AT80604004887AA User Manual

Product codes
AT80604004887AA
Page of 172
Intel® Xeon® Processor 7500 Datasheet, Volume 1
159
Features
7.5.3.2
RES3: Reserved 3
This locations are reserved. Writes to this register have no effect.
7.5.3.3
MP1CF: Maximum P1 Core Frequency
This location contains the maximum non-Turbo Boost core frequency for the processor. 
The frequency should equate to the markings on the processor and/or the QDF/S-spec 
speed even if the parts are not limited or locked to the intended speed. Format of this 
field is in MHz, rounded to a whole number, and encoded in binary coded decimal. 
Writes to this register have no effect.
Example: A 2.666 GHz processor will have a value of 2666h.
7.5.3.4
MP0CF: Maximum P0 Core Frequency
This location contains the maximum Turbo Boost core frequency for the processor. This 
is the maximum intended speed for the part under any functional conditions. Format of 
this field is in MHz, rounded to a whole number, and encoded in binary coded decimal. 
Writes to this register have no effect.
Example: A processor with a maximum Turbo Boost frequency of 2.666 GHz will have 
a value of 2666h.
7.5.3.5
MAXVID: Maximum Core VID
This location contains the maximum Core VID (Voltage Identification) voltage that may 
be requested via the VID pins. This field, rounded to the next thousandth, is in mV and 
is reflected in binary coded decimal. Writes to this register have no effect.
Example: A voltage of 1.350 V maximum core VID would contain 1350h.
Offset:
1Dh-1Eh
Bit
Description
15:0
RESERVED
0000h-FFFFh: Reserved
Offset:
1F-20h
Bit
Description
15:0
Maximum P1 Core Frequency
0000h-FFFFh: MHz
Offset:
21h-22h
Bit
Description
15:0
Maximum P0 Core Frequency
0000h-FFFFh: MHz