Intel E7520 AT80604004887AA User Manual
Product codes
AT80604004887AA
Intel® Xeon® Processor 7500 Datasheet, Volume 1
35
Electrical Specifications
2.5.2.2
Requirements for 4.8 GT/s and 6.4 GT/s
Electrical specifications for Tx and Rx for 4.8 GT/s are captured in
and for
.
Table 2-13. Parameter Values for Intel® QPI Channel at 4.8 GT/s (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Notes
V
Tx-diff-pp-pin
Transmitter differential swing
800
1500
mV
1
Z
TX_LOW_CM_DC
DC resistance of Tx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
pin
) bias point
38
47
Ω
Z
RX_LOW_CM_DC
DC resistance of Rx terminations
at half the single ended swing
(which is usually 0.25*V
Tx-diff-pp-
pin
) bias point
38
47
Ω
V
Tx-cm-dc-pin
Transmitter output DC common
mode, defined as average of V
D+
and V
D-
0.23
0.27
Fraction of
V
Tx-diff-pp-pin
V
Tx-cm-ac-pin
Transmitter output AC common
mode, defined as ((V
D+
+ V
D-
)/2 -
V
Tx-cm-dc-pin
)
-
0.0375
0.0375
Fraction of
V
Tx-diff-pp-pin
2
TX
duty-pin
Average of UI-UI jitter.
-0.025
0.03
UI
TX
jitUI-UI-1E-7-pin
UI-UI jitter measured at Tx output
pins with 1E-7 probability.
-0.065
0.07
UI
3
TX
jitUI-UI-1E-9-pin
UI-UI jitter measured at Tx output
pins with 1E-9 probability.
-0.07
0.076
UI
TX
clk-acc-jit-N_UI-1E-7
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-7
probability.
0
0.15
UI
TX
clk-acc-jit-N_UI-1E-9
p-p accumulated jitter out of
transmitter over 0 <= n <= N UI
where N=12, measured with 1E-9
probability.
0
0.17
UI
T
Tx-data-clk-skew-pin
Delay of any data lane relative to
clock lane, as measured at Tx
output
-0.5
0.5
UI
V
Rx-diff-pp-pin
Voltage eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9
(UI).
225
1200
mV
T
Rx-diff-pp-pin
Timing eye opening at the end of
Tx+ channel for any data or clock
channel measured with a
cumulative probability of 1E-9 (UI)
0.63
1
UI
T
Rx-data-clk-skew-pin
Delay of any data lane relative to
the clock lane, as measured at the
end of Tx+ channel. This
parameter is a collective sum of
effects of data clock mismatches
in Tx and on the medium
connecting Tx and Rx.
-1
4
UI