Intel E7520 AT80604004887AA User Manual

Intel® Xeon® Processor 7500 Datasheet, Volume 1

43

1.

Specified at the package pins into a timing and voltage compliant test setup.

2.

The V

RX-DIFFp-p

 pin specification reflects a target eye height at the pad equal to 70 mV.

3.

Specified at the package pins into a timing and voltage compliance test setup.

4.

The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply with both the 

single-pulse mask and the cumulative eye mask.

5.

The relative amplitude ratio limit between adjacent symbols prevents excessive inter-symbol interference in the Rx. Each 

symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols.

6.

This number does not include the effects of SSC or reference clock jitter.

7.

The T

RX-Eye-MIN

 pin specification reflects a target eye width at the pad equal to 0.45 UI.

8.

The T

RX-DJ-DD

 pin specification reflects a target max deterministic jitter at the pad equal to 0.45 UI.

9.

Defined as the dual-dirac deterministic jitter at the receiver input.

10. Allows for 15 mV DC offset between transmit and receive devices.

11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-to-peak common mode 

specification. For example, if V

RX-DIFFp-p

 is 200 mV, the maximum AC peak-to-peak common mode is the lesser of 

(200 mV * 0.45 = 90 mV) and V

RX-CM-ACp-p

.

12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully 

designed. 

13. The termination small signal resistance; tolerance over the entire signaling voltage range shall not exceed ± 5 Ω.

14. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage 

and temperature ranges for a single component. Drift rate of change is significantly below the tracking capability of the 

receiver.

V

RX-CM-EH-Ratio

Ratio of V

RX-DIFFp-p

 increase to max 

DC common mode increase (V

RX-

DIFFp-p

 > V

RX-DIFFp-p-min

)

1

V

RX-DIFFp-p

 >= V

RX-DIFFp-p-min

 +

V

RX-CM-EH-Ratio

 * (V

RX-CM

 - 310 mV)

V

RX-CM-ABS

Common mode of the input voltage 

(Absolute max)

375

mV

V

RX-CM = 

DC

(avg)

 of |V

RX-D+ 

+ V

RX-D-

|/2 

V

RX-CM-ACp-p

AC peak-to-peak common mode of 

input voltage

270

mV

V

RX-CM-AC 

=

Max |V

RX-D+ 

+ V

RX-D-

|/2–

Min |V

RX-D+ 

+ V

RX-D-

|/2

Measured as: 

V

RX-CM-AC-EH-Ratio

Ratio of V

RX-CM-ACp-p

 to minimum 

V

RX-DIFFp-p

45

%

RL

RX-DIFF

Differential return loss

9

dB

Measured over 0.1GHz to 3.2 GHz. 

See also 

RL

RX-CM

Common mode return loss

6

dB

Measured over 0.1GHz to 3.2 GHz. 

See also 

R

RX

RX termination resistance

37.4

47.6

Ohm

T

RX-SKEW-CLK-DATA

RX skew between clock and data

0.0

1.0

ns

Forwarded clock delay - data delay

T

RX-DRIFT

Minimum RX Drift Tolerance

600

ps

T

FR-ENTRY -DETECT

Fast reset entry detect time

240

UI

BER

Bit Error Ratio

10

-12