Intel LF80550KF0604M Data Sheet

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

93

To maintain backward compatibility, the Header defines the starting address for each 
subsequent section of the PIROM. Software should check for the offset before reading 
data from a particular section of the ROM. 

Example: Code looking for the cache data of a processor would read offset 05h to find 
a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM.

This location identifies the data format revision of the PIROM data structure. Writes to 
this register have no effect.

This location identifies the PIROM size. Writes to this register have no effect.

This location provides the offset to the Processor Data Section. Writes to this register 
have no effect.

7:0

The data format revision is used whenever fields within the PIROM are 

redefined. The initial definition will begin at a value of 1. If a field, or bit 

assignment within a field, is changed such that software needs to discern 

between the old and new definition, then the data format revision field will be 

incremented.

00h:  Reserved

01h: Initial 

definition

02h:  Second revision

03h:  Third revision (Defined by this EMTS)

04h-FFh: Reserved

15:0

The PIROM size provides the size of the device in hex bytes. The MSB is at 

location 01h, the LSB is at location 02h.

0000h - 007Fh: Reserved

0080h: 128 byte PIROM size

0081- FFFFh: Reserved

7:0

Byte pointer to the Processor Data section

00h: Processor Data section not present

01h - 0Dh: Reserved

0Eh: Processor Data section pointer value

0Fh-FFh: Reserved