Intel LF80550KF0604M User Manuals

Table of Contents

• 1 Introduction

  11
  • 1.1 Terminology

    13
  • 1.2 References

    14
  • 1.3 State of Data

    15
• 2 Electrical Specifications

  17
  • 2.1 Front Side Bus and GTLREF

    17
    • 2.1.1 Front Side Bus Clock and Processor Clocking

      18
    • 2.1.2 Front Side Bus Clock Select (BSEL[1:0])

      19
    • 2.1.3 Phase Lock Loop (PLL) Power and Filter

      20
  • 2.2 Voltage Identification (VID)

    21
  • 2.3 Cache Voltage Identification (CVID)

    22
  • 2.4 Reserved, Unused, and TESTHI Pins

    23
  • 2.5 Mixing Processors

    24
  • 2.6 Front Side Bus Signal Groups

    24
  • 2.7 GTL+ Asynchronous and AGTL+ Asynchronous Signals

    26
  • 2.8 Test Access Port (TAP) Connection

    27
  • 2.9 Maximum Ratings

    27
  • 2.10 Processor DC Specifications

    28
    • 2.10.1 Flexible Motherboard (FMB) Guidelines

      28
    • 2.10.2 VCC Overshoot Specification

      34
    • 2.10.3 VCACHE Overshoot Specification

      35
    • 2.10.4 Die Voltage Validation

      36
    • 2.10.5 Clock, Miscellaneous and AGTL+ Specifications

      36
  • 2.11 AGTL+ Front Side Bus Specifications

    40
• 3 Mechanical Specifications

  41
  • 3.1 Package Mechanical Drawing

    42
  • 3.2 Processor Component Keep-Out Zones

    45
  • 3.3 Package Loading Specifications

    45
  • 3.4 Package Handling Guidelines

    46
  • 3.5 Package Insertion Specifications

    46
  • 3.6 Processor Mass Specifications

    46
  • 3.7 Processor Materials

    46
  • 3.8 Processor Markings

    46
  • 3.9 Processor Pin-Out Coordinates

    48
• 4 Pin Listing

  49
  • 4.1 Dual-Core Intel® Xeon® Processor 7100 Series Pin Assignments

    49
    • 4.1.1 Pin Listing by Pin Name

      49
    • 4.1.2 Pin Listing by Pin Number

      57
• 5 Signal Definitions

  65
  • 5.1 Signal Definitions

    65
• 6 Thermal Specifications

  73
  • 6.1 Package Thermal Specifications

    73
    • 6.1.1 Thermal Specifications

      73
    • 6.1.2 Thermal Metrology

      77
  • 6.2 Processor Thermal Features

    77
    • 6.2.1 Thermal Monitor

      77
    • 6.2.2 Thermal Monitor 2

      78
    • 6.2.3 On-Demand Mode

      79
    • 6.2.4 PROCHOT# Signal Pin

      80
    • 6.2.5 FORCEPR# Signal Pin

      80
    • 6.2.6 THERMTRIP# Signal Pin

      80
    • 6.2.7 TCONTROL and Fan Speed Reduction

      80
    • 6.2.8 Thermal Diode

      81
• 7 Features

  83
  • 7.1 Power-On Configuration Options

    83
  • 7.2 Clock Control and Low Power States

    83
    • 7.2.1 Normal State

      84
    • 7.2.2 HALT or Enhanced Power Down State

      84
    • 7.2.3 Stop-Grant State

      85
    • 7.2.4 Enhanced HALT Snoop State or HALT Snoop State, Stop Grant Snoop State

      86
  • 7.3 Enhanced Intel SpeedStep® Technology

    86
  • 7.4 System Management Bus (SMBus) Interface

    87
    • 7.4.1 SMBus Device Addressing

      88
    • 7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions

      90
    • 7.4.3 Processor Information ROM (PIROM)

      90
    • 7.4.4 Checksums

      109
    • 7.4.5 Scratch EEPROM

      110
    • 7.4.6 SMBus Thermal Sensor

      110
    • 7.4.7 Thermal Sensor Supported SMBus Transactions

      111
    • 7.4.8 SMBus Thermal Sensor Registers

      113
    • 7.4.9 SMBus Thermal Sensor Alert Interrupt

      116
• 8 Boxed Processor Specifications

  117
  • 8.1 Introduction

    117
  • 8.2 Mechanical Specifications

    118
    • 8.2.1 Boxed Processor Heatsink Dimensions

      118
    • 8.2.2 Boxed Processor Heatsink Weight

      125
    • 8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports

      125
  • 8.3 Thermal Specifications

    125
    • 8.3.1 Boxed Processor Cooling Requirements

      125
    • 8.3.2 Boxed Processor Contents

      126
• 9 Debug Tools Specifications

  127
  • 9.1 Logic Analyzer Interface (LAI)

    127
    • 9.1.1 Mechanical Considerations

      127
    • 9.1.2 Electrical Considerations

      127