Intel AT80604004881AA User Manual

Intel® Xeon® Processor 7500 Datasheet, Volume 1

151

The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However, 
since the PIROM is write-protected, it will acknowledge a Write Byte command but 
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte 
commands. 

 

illustrates the Read Byte command. 

illustrates the 

Write Byte command. 

In the tables, ‘S’ represents a SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents 
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The 
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t 
shaded are transmitted by the SMBus host controller. In the tables, the data addresses 
indicate 8 bits.

The SMBus host controller should transmit 8 bits with the most significant bit indicating 
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch 
EEPROM (MSB = 1).

Of the addresses broadcast across the SMBus, the memory component claims those of 
the form “10100XXZb”. The “XX” bits are defined by pull-up and pull-down of the 
SKTID[1:0] pins. Note that SKTID[2] does not affect the SMBus address for the 
memory component. These address pins are pulled down weakly (10 k) on the 
processor substrate to ensure that the memory components are in a known state in 
systems which do not support the SMBus (or only support a partial implementation). 
The “Z” bit is the read/write bit for the serial bus transaction.

Note that addresses of the form “0000XXXXb” are Reserved and should not be 
generated by an SMBus master. 

 describes the address pin connections and how they affect the addressing of 

the memory component.

1

7-bits

1

1

8-bits

1

1

7-bits

1

1

8-bits

1

1

1

7-bits

1

1

8-bits

1

8-bits

1

1