Intel AT80604004881AA User Manual
Features
152
Intel® Xeon® Processor 7500 Datasheet, Volume 1
Note:
1.
This addressing scheme will support up to 4 processors on a single SMBus.
7.5
Managing Data in the PIROM
The PIROM consists of the following sections:
• Header
• Processor Data
• Processor Core Data
• Processor Uncore Data
• Cache Data
• Package Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data
• Processor Data
• Processor Core Data
• Processor Uncore Data
• Cache Data
• Package Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data
Details on each of these sections are described below.
Note:
Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not
rely on this model.
7.5.1
Header
To maintain backward compatibility, the Header defines the starting address for each
subsequent section of the PIROM. Software should check for the offset before reading
data from a particular section of the ROM.
subsequent section of the PIROM. Software should check for the offset before reading
data from a particular section of the ROM.
Example: Code looking for the processor uncore data of a processor would read offset
05h to find a value of 29. 29 is the first address within the 'Processor Uncore Data'
section of the PIROM.
05h to find a value of 29. 29 is the first address within the 'Processor Uncore Data'
section of the PIROM.
7.5.1.1
DFR: Data Format Revision
This location identifies the data format revision of the PIROM data structure. Writes to
this register have no effect.
this register have no effect.
Table 7-4.
Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
1
Device Select
R/W
Bits 7-4
SKTID[2]
SKTID[1]
Bit 2
SKTID[0]
Bit 1
Bit 0
A0h/A1h
10100
10100
0
0
X
A2h/A3h
10100
10100
0
1
X
A4h/A5h
10100
10100
1
0
X
A6h/A7h
10100
10100
1
1
X