Intel AT80604004881AA User Manual

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Intel® Xeon® Processor 7500 Datasheet, Volume 1

The Flexible Motherboard (FMB) guidelines are estimates of the maximum ratings that 
the Intel® Xeon® processor 7500 series will have over certain time periods. The 
ratings are only estimates as actual specifications for future processors may differ. The 
VR 11.1 specification is developed to meet FMB Voltage Specification values required by 
all Intel® Xeon® processor 7500 series SKUs. 

All Reserved signals must be left unconnected on the motherboard. Any deviation in 
connection of these signals to any power rail or other signals can result in component 
malfunction or incompatibility with future processors. See 

 for socket land 

listing of the processor and the location of all signals, including RSVD signals.

Unused Intel® QPI or Intel® SMI input ports may be left as no-connects.

The recommended TAP connectivity will be detailed in an upcoming document release.

Intel supports and validates multiple processor configurations only in which all 
processors operate with the same Intel® QPI frequency, core frequency, power 
segment, have the same number of cores, and have the same internal cache sizes. 
Mixing components operating at different internal clock frequencies is not supported 
and will not be validated by Intel. Combining processors from different power segments 
is also not supported.

The processor SPD Interface is used for memory initialization including the set up and 
use of the memory thermal sensor on-board the Intel® 7500 Scalable Memory Buffer. 
Base board management controllers (BMC) can use the PECI interface to the SPD 
engine for access to this thermal data.

The SPD master in the processor supports 100 khz operation and the following set of 
commands:

Send Byte and Receive Byte

Write Byte and Read Byte

Write Word and Read Word

The SPD Interface does not support bus arbitration or clock stretching.