Intel E3-1275 CM8062307262003 User Manual
Product codes
CM8062307262003
6
Datasheet, Volume 1
Figures
1-1
Intel
®
Xeon
®
Processor E3-1200 Family Platform ........................................................10
2-1
Intel
®
Flex Memory Technology Operation ..................................................................23
2-2
PCI Express* Layering Diagram.................................................................................26
2-3
Packet Flow through the Layers.................................................................................26
2-4
PCI Express* Related Register Structures in the Processor ............................................28
2-5
PCIe Typical Operation 16 lanes Mapping....................................................................29
2-6
Processor Graphics Controller Unit Block Diagram ........................................................30
2-7
Processor Display Block Diagram ...............................................................................33
4-1
Power States ..........................................................................................................45
4-2
Idle Power Management Breakdown of the Processor Cores ..........................................49
4-3
Thread and Core C-State Entry and Exit .....................................................................49
4-4
Package C-State Entry and Exit .................................................................................53
7-1
Example for PECI Host-clients Connection...................................................................87
7-2
Input Device Hysteresis ...........................................................................................88
8-1
Socket Pinmap (Top View, Upper-Left Quadrant) .........................................................90
8-2
Socket Pinmap (Top View, Upper-Right Quadrant) .......................................................91
8-3
Socket Pinmap (Top View, Lower-Left Quadrant) .........................................................92
8-4
Socket Pinmap (Top View, Lower-Right Quadrant) .......................................................93
Tables
1-1
PCIe Supported Configurations in Server/Workstation Products .....................................12
1-2
Related Documents .................................................................................................19
2-1
Supported UDIMM Module Configurations ...................................................................21
2-2
DDR3 System Memory Timing Support.......................................................................22
2-3
Reference Clock ......................................................................................................35
4-1
System States ........................................................................................................46
4-2
Processor Core/Package State Support .......................................................................46
4-3
Integrated Memory Controller States .........................................................................46
4-4
PCIe Link States......................................................................................................46
4-5
DMI States .............................................................................................................47
4-6
Processor Graphics Controller States..........................................................................47
4-7
G, S, and C State Combinations ................................................................................47
4-8
Coordination of Thread Power States at the Core Level .................................................50
4-9
P_LVLx to MWAIT Conversion....................................................................................50
4-10 Coordination of Core Power States at the Package Level ...............................................52
6-1
6-1
Signal Description Buffer Types .................................................................................63
6-2
Memory Channel A ..................................................................................................64
6-3
Memory Channel B ..................................................................................................65
6-4
Memory Reference and Compensation ........................................................................65
6-5
Reset and Miscellaneous Signals................................................................................66
6-6
PCI Express* Graphics Interface Signals .....................................................................67
6-7
Intel® Flexible Display Interface ...............................................................................67
6-8
DMI - Processor to PCH Serial Interface......................................................................67
6-9
PLL Signals.............................................................................................................68
6-10 TAP Signals ............................................................................................................68
6-11 Error and Thermal Protection ....................................................................................69
6-12 Power Sequencing ...................................................................................................69
6-13 Processor Power Signals ...........................................................................................70
6-14 Sense Pins .............................................................................................................70
6-15 Ground and NCTF ....................................................................................................70
6-16 Processor Internal Pull Up/Pull Down..........................................................................71
7-1
6-11 Error and Thermal Protection ....................................................................................69
6-12 Power Sequencing ...................................................................................................69
6-13 Processor Power Signals ...........................................................................................70
6-14 Sense Pins .............................................................................................................70
6-15 Ground and NCTF ....................................................................................................70
6-16 Processor Internal Pull Up/Pull Down..........................................................................71
7-1
VR 12.0 Voltage Identification Definition.....................................................................75
7-2
VCCSA_VID configuration .........................................................................................78