Intel E3-1275 User Manuals

Table of Contents

• Introduction

  9
• Intel® Xeon® Processor E3-1200 Family Platform

  10
• Processor Feature Details

  11
• 1.1.1 Supported Technologies

  11
• Interfaces

  11
• 1.2.1 System Memory Support

  11
• 1.2.2 PCI Express*

  12
• PCIe Supported Configurations in Server/Workstation Products

  12
• 1.2.3 Direct Media Interface (DMI)

  14
• 1.2.4 Platform Environment Control Interface (PECI)

  14
• 1.2.5 Processor Graphics

  15
• 1.2.6 Intel® Flexible Display Interface (Intel® FDI)

  15
• Power Management Support

  16
• 1.3.1 Processor Core

  16
• 1.3.2 System

  16
• 1.3.3 Memory Controller

  16
• 1.3.4 PCI Express*

  16
• 1.3.5 DMI

  16
• 1.3.6 Processor Graphics Controller

  16
• Thermal Management Support

  16
• Package

  17
• Terminology

  17
• Related Documents

  19
• Related Documents

  19
• Interfaces

  21
• System Memory Interface

  21
• 2.1.1 System Memory Technology Supported

  21
• Supported UDIMM Module Configurations

  21
• 2.1.2 System Memory Timing Support

  22
• DDR3 System Memory Timing Support

  22
• 2.1.3 System Memory Organization Modes

  23
• 2.1.3.1 Single-Channel Mode

  23
• 2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

  23
• Intel® Flex Memory Technology Operation

  23
• 2.1.4 Rules for Populating Memory Slots

  24
• 2.1.5 Technology Enhancements of Intel ® Fast Memory Access (Intel® FMA)

  24
• 2.1.5.1 Just-in-Time Command Scheduling

  24
• 2.1.5.2 Command Overlap

  24
• 2.1.5.3 Out-of-Order Scheduling

  25
• 2.1.6 Memory Type Range Registers (MTRRs) Enhancement

  25
• 2.1.7 Data Scrambling

  25
• PCI Express* Interface

  25
• 2.2.1 PCI Express* Architecture

  25
• PCI Express* Layering Diagram

  26
• Packet Flow through the Layers

  26
• 2.2.1.1 Transaction Layer

  27
• 2.2.1.2 Data Link Layer

  27
• 2.2.1.3 Physical Layer

  27
• 2.2.2 PCI Express* Configuration Mechanism

  28
• 2.2.3 PCI Express* Port

  28
• PCI Express* Related Register Structures in the Processor

  28
• 2.2.4 PCI Express Lanes Connection

  29
• Direct Media Interface (DMI)

  29
• 2.3.1 DMI Error Flow

  29
• 2.3.2 Processor/PCH Compatibility Assumptions

  29
• PCIe Typical Operation 16 lanes Mapping

  29
• 2.3.3 DMI Link Down

  30
• Processor Graphics Controller (GT)

  30
• Processor Graphics Controller Unit Block Diagram

  30
• 2.4.1 3D and Video Engines for Graphics Processing

  31
• 2.4.1.1 3D Engine Execution Units

  31
• 2.4.1.2 3D Pipeline

  31
• 2.4.1.3 Video Engine

  32
• 2.4.1.4 2D Engine

  32
• 2.4.2 Processor Graphics Display

  33
• 2.4.2.1 Display Planes

  33
• Processor Display Block Diagram

  33
• 2.4.2.2 Display Pipes

  34
• 2.4.2.3 Display Ports

  34
• 2.4.3 Intel® Flexible Display Interface

  34
• 2.4.4 Multi-Graphics Controller Multi-Monitor Support

  34
• Platform Environment Control Interface (PECI)

  35
• Interface Clocking

  35
• 2.6.1 Internal Clocking Requirements

  35
• Reference Clock

  35
• 3.1 Intel® Virtualization Technology

  37
• 3.1.1 Intel® VT-x Objectives

  37
• 3.1.2 Intel® VT-x Features

  38
• 3.1.3 Intel® VT-d Objectives

  38
• 3.1.4 Intel® VT-d Features

  38
• 3.1.5 Intel® VT-d Features Not Supported

  39
• 3.2 Intel® Trusted Execution Technology (Intel ® TXT)

  40
• 3.3 Intel® Hyper-Threading Technology

  40
• 3.4 Intel® Turbo Boost Technology

  41
• 3.4.1 Intel® Turbo Boost Technology Frequency

  41
• 3.4.2 Intel® Turbo Boost Technology Graphics Frequency

  41
• 3.5 Intel® Advanced Vector Extensions (AVX)

  42
• 3.6 Advanced Encryption Standard New Instructions (AES-NI)

  42
• 3.6.1 PCLMULQDQ Instruction

  42
• 3.7 Intel® 64 Architecture x2APIC

  42
• Power States

  45
• 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

  46
• 4.1.1 System States

  46
• 4.1.2 Processor Core/Package Idle States

  46
• 4.1.3 Integrated Memory Controller States

  46
• 4.1.4 PCIe Link States

  46
• System States

  46
• Processor Core/Package State Support

  46
• Integrated Memory Controller States

  46
• PCIe Link States

  46
• 4.1.5 DMI States

  47
• 4.1.6 Processor Graphics Controller States

  47
• 4.1.7 Interface State Combinations

  47
• DMI States

  47
• Processor Graphics Controller States

  47
• G, S, and C State Combinations

  47
• 4.2 Processor Core Power Management

  48
• 4.2.1 Enhanced Intel® SpeedStep® Technology

  48
• 4.2.2 Low-Power Idle States

  48
• Idle Power Management Breakdown of the Processor Cores

  49
• Thread and Core C-State Entry and Exit

  49
• 4.2.3 Requesting Low-Power Idle States

  50
• Coordination of Thread Power States at the Core Level

  50
• P_LVLx to MWAIT Conversion

  50
• 4.2.4 Core C-states

  51
• 4.2.4.1 Core C0 State

  51
• 4.2.4.2 Core C1/C1E State

  51
• 4.2.4.3 Core C3 State

  51
• 4.2.4.4 Core C6 State

  51
• 4.2.4.5 C-State Auto-Demotion

  51
• 4.2.5 Package C-States

  52
• Coordination of Core Power States at the Package Level

  52
• 4.2.5.1 Package C0

  53
• 4.2.5.2 Package C1/C1E

  53
• Package C-State Entry and Exit

  53
• 4.2.5.3 Package C3 State

  54
• 4.2.5.4 Package C6 State

  54
• 4.3 IMC Power Management

  54
• 4.3.1 Disabling Unused System Memory Outputs

  54
• 4.3.2 DRAM Power Management and Initialization

  55
• 4.3.2.1 Initialization Role of CKE

  56
• 4.3.2.2 Conditional Self-Refresh

  56
• 4.3.2.3 Dynamic Power-down Operation

  57
• 4.3.2.4 DRAM I/O Power Management

  57
• PCIe* Power Management

  57
• DMI Power Management

  57
• Graphics Power Management

  58
• (also known as CxSR)

  58
• 4.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)

  58
• 4.6.3 Graphics Render C-State

  58
• 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

  58
• 4.6.5 Intel® Graphics Dynamic Frequency

  59
• Thermal Power Management

  59
• Thermal Management

  61
• Signal Description

  63
• Signal Description Buffer Types

  63
• System Memory Interface

  64
• Memory Channel A

  64
• Memory Reference and Compensation

  65
• Memory Channel B

  65
• Memory Reference and Compensation

  65
• Reset and Miscellaneous Signals

  66
• Reset and Miscellaneous Signals

  66
• PCI Express* Based Interface Signals

  67
• Intel® Flexible Display Interface Signals

  67
• DMI

  67
• PCI Express* Graphics Interface Signals

  67
• Intel® Flexible Display Interface

  67
• DMI - Processor to PCH Serial Interface

  67
• PLL Signals

  68
• TAP Signals

  68
• PLL Signals

  68
• TAP Signals

  68
• Error and Thermal Protection

  69
• 6.10 Power Sequencing

  69
• Error and Thermal Protection

  69
• Power Sequencing

  69
• 6.11 Processor Power Signals

  70
• 6.12 Sense Pins

  70
• 6.13 Ground and NCTF

  70
• Processor Power Signals

  70
• Sense Pins

  70
• Ground and NCTF

  70
• 6.14 Processor Internal Pull Up/Pull Down

  71
• Processor Internal Pull Up/Pull Down

  71
• Electrical Specifications

  73
• Power and Ground Lands

  73
• Decoupling Guidelines

  73
• 7.2.1 Voltage Rail Decoupling

  73
• Processor Clocking (BCLK[0], BCLK#[0])

  74
• 7.3.1 PLL Power Supply

  74
• VCC Voltage Identification (VID)

  74
• VR 12.0 Voltage Identification Definition

  75
• System Agent (SA) VCC VID

  78
• Reserved or Unused Signals

  78
• VCCSA_VID configuration

  78
• Signal Groups

  79
• Signal Groups 1

  79
• Test Access Port (TAP) Connection

  80
• Storage Conditions Specifications

  81
• Storage Condition Ratings

  81
• 7.10 DC Specifications

  82
• 7.10.1 Voltage and Current Specifications

  82
• Processor Core Active and Idle Mode DC Voltage and Current Specifications

  82
• Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications

  83
• Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications

  84
• DDR3 Signal Group DC Specifications

  84
• Control Sideband and TAP Signal Group DC Specifications

  85
• PCIe DC Specifications

  86
• 7.11 Platform Environmental Control Interface (PECI) DC Specifications

  87
• 7.11.1 PECI Bus Architecture

  87
• Example for PECI Host-clients Connection

  87
• 7.11.2 DC Characteristics

  88
• 7.11.3 Input Device Hysteresis

  88
• Input Device Hysteresis

  88
• PECI DC Electrical Limits

  88
• Processor Pin and Signal Information

  89
• 8.1 Processor Pin Assignments

  89
• Socket Pinmap (Top View, Upper-Left Quadrant)

  90
• Socket Pinmap (Top View, Upper-Right Quadrant)

  91
• Socket Pinmap (Top View, Lower-Left Quadrant)

  92
• Socket Pinmap (Top View, Lower-Right Quadrant)

  93
• Processor Pin List by Pin Name

  94
• DDR Data Swizzling

  109
• DDR Data Swizzling Table – Channel A

  110
• DDR Data Swizzling Table – Channel B

  111