Intel E3-1275 CM8062307262003 User Manual
Product codes
CM8062307262003
Electrical Specifications
84
Datasheet, Volume 1
Notes:
1.
1.
V
CCAXG
is VID based rail.
2.
Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
3.
The V
AXG_MIN
and V
AXG_MAX
loadlines represent static and transient limits.
4.
The loadlines specify voltage limits at the die measured at the VAXG_SENSE and VSSAXG_SENSE lands.
Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG_SENSE
and VSSAXG_SENSE lands.
Voltage regulation feedback for voltage regulator circuits must also be taken from processor VAXG_SENSE
and VSSAXG_SENSE lands.
5.
PSx refers to the voltage regulator power state as set by the SVID protocol.
6.
Each processor is programmed with a maximum valid voltage identification value (VID) that is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
Table 7-7.
Processor Graphics VID based (V
AXG
) Supply DC Voltage and Current
Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
2
V
AXG
GFX_VID
Range
GFX_VID Range for V
CCAXG
0.2500
1.5200
V
1
LL
AXG
V
CCAXG
Loadline Slope
4.1
m
3, 4
V
AXG
TOB
V
CC
Tolerance Band
PS0, PS1
PS2
PS2
19
11.5
mV
3, 4, 5
V
AXG
Ripple
Ripple:
PS0
PS1
PS2
PS1
PS2
±10
±10
±10
-10/+15
mV
3, 4, 5
I
AXG
Current for Processor Graphics
core
core
35
A
I
AXG_TDC
Sustained current for Processor
Graphics core
Graphics core
25
A
Table 7-8.
DDR3 Signal Group DC Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes
1,9
V
IL
Input Low Voltage
SM_VREF 0.1
V
2,4
V
IH
Input High Voltage
SM_VREF + 0.1
V
3
V
OL
Output Low Voltage
(V
DDQ
/ 2)* (R
ON
/(R
ON
+R
TERM
))
6
V
OH
Output High Voltage
V
DDQ
((V
DDQ
/ 2)*
(R
ON
/(R
ON
+R
TERM
))
V
4,6
R
ON_UP(DQ)
DDR3 data buffer pull-up
resistance
resistance
24.31
28.6
32.9
5
R
ON_DN(DQ)
DDR3 data buffer pull-down
resistance
resistance
22.88
28.6
34.32
5
R
ODT(DQ)
DDR3 on-die termination
equivalent resistance for data
signals
equivalent resistance for data
signals
83
41.5
100
50
117
65
7
V
ODT(DC)
DDR3 on-die termination DC
working point (driver set to
receive mode)
working point (driver set to
receive mode)
0.43*V
DDQ
0.5*V
DDQ
0.56*V
CC
V
7
R
ON_UP(CK)
DDR3 clock buffer pull-up
resistance
resistance
20.8
26
28.6
5
R
ON_DN(CK)
DDR3 clock buffer pull-down
resistance
resistance
20.8
26
31.2
5