AMD amd64 architecture User Manual
178
128-Bit Media and Scientific Programming
AMD64 Technology
24592—Rev. 3.15—November 2009
A device-not-available exception (#NM) can occur if an attempt is made to execute a 128-bit media
instruction when the task switch bit (TS) of the control register (CR0) is set to 1 (CR0.TS = 1).
instruction when the task switch bit (TS) of the control register (CR0) is set to 1 (CR0.TS = 1).
An invalid-opcode exception (#UD) can occur if:
•
a CPUID feature flag indicates that a feature is not supported (see “Feature Detection” on
page 176), or
page 176), or
•
an FXSAVE or FXRSTOR instruction is executed when the floating-point software-emulation
(EM) bit in control register 0 is set to 1 (CR0.EM = 1), or
(EM) bit in control register 0 is set to 1 (CR0.EM = 1), or
•
a SIMD floating-point exception occurs when the operating-system XMM exception support bit
(OSXMMEXCPT) in control register 4 is cleared to 0 (CR4.OSXMMEXCPT = 0).
(OSXMMEXCPT) in control register 4 is cleared to 0 (CR4.OSXMMEXCPT = 0).
Only the following 128-bit media instructions, all of which can access an MMX register, can cause an
#MF exception:
#MF exception:
•
Data Conversion: CVTPD2PI, CVTPS2PI, CPTPI2PD, CVTPI2PS, CVTTPD2PI, CVTTPS2PI.
•
Data Transfer: MOVDQ2Q, MOVQ2DQ.
For details on the system control-register bits, see “System-Control Registers” in Volume 2. For details
on the machine-check mechanism, see “Machine Check Mechanism” in Volume 2.
on the machine-check mechanism, see “Machine Check Mechanism” in Volume 2.
For details on #XF exceptions, see “SIMD Floating-Point Exception Causes” on page 178.
Exceptions Not Generated.
The 128-bit media instructions do not generate the following general-
purpose exceptions:
•
#DE—Divide-by-zero-error exception (Vector 0)
•
Non-Maskable-Interrupt Exception (Vector 2)
•
#BP—Breakpoint Exception (Vector 3)
•
#OF—Overflow exception (Vector 4)
•
#BR—Bound-range exception (Vector 5)
•
Coprocessor-segment-overrun exception (Vector 9)
•
#TS—Invalid-TSS exception (Vector 10)
•
#NP—Segment-not-present exception (Vector 11)
•
#MC—Machine-check exception (Vector 18)
For details on all general-purpose exceptions, see “Exceptions and Interrupts” in Volume 2.
4.10.2 SIMD Floating-Point Exception Causes
The SIMD floating-point exception is the logical OR of the six floating-point exceptions (IE, DE, ZE,
OE, UE, PE) that are reported (signalled) in the MXCSR register’s exception flags (“MXCSR
Register” on page 117). Each of these six exceptions can be either masked or unmasked by software,
using the mask bits in the MXCSR register.
OE, UE, PE) that are reported (signalled) in the MXCSR register’s exception flags (“MXCSR
Register” on page 117). Each of these six exceptions can be either masked or unmasked by software,
using the mask bits in the MXCSR register.