AMD amd64 architecture User Manual
232
64-Bit Media Programming
AMD64 Technology
24592—Rev. 3.15—November 2009
processor asserts the FERR# output signal. For details about the x87 floating-point exceptions and the
FERR# output signal, see “x87 Floating-Point Exception Causes” on page 279.
FERR# output signal, see “x87 Floating-Point Exception Causes” on page 279.
5.12
Actions Taken on Executing 64-Bit Media Instructions
The MMX registers are mapped onto the low 64 bits of the 80-bit x87 floating-point physical registers,
FPR0–FPR7, described in “Registers” on page 238. The MMX instructions do not use the x87 stack-
addressing mechanism. However, 64-bit media instructions write certain values in the x87 top-of-stack
pointer, tag bits, and high bits of the FPR0–FPR7 data registers.
FPR0–FPR7, described in “Registers” on page 238. The MMX instructions do not use the x87 stack-
addressing mechanism. However, 64-bit media instructions write certain values in the x87 top-of-stack
pointer, tag bits, and high bits of the FPR0–FPR7 data registers.
Specifically, the processor performs the following x87-related actions atomically with the execution of
64-bit media instructions:
64-bit media instructions:
•
Top-Of-Stack Pointer (TOP)—The processor clears the x87 top-of-stack pointer (bits 13–11 in the
x87 status word register) to all 0s during the execution of every 64-bit media instruction, causing it
to point to the mmx0 register.
x87 status word register) to all 0s during the execution of every 64-bit media instruction, causing it
to point to the mmx0 register.
•
Tag Bits—During the execution of every 64-bit media instruction, except the EMMS and FEMMS
instructions, the processor changes the tag state for all eight MMX registers to full, as described
below. In the case of EMMS and FEMMS, the processor changes the tag state for all eight MMX
registers to empty, thus initializing the stack for an x87 floating-point procedure.
instructions, the processor changes the tag state for all eight MMX registers to full, as described
below. In the case of EMMS and FEMMS, the processor changes the tag state for all eight MMX
registers to empty, thus initializing the stack for an x87 floating-point procedure.
•
Bits 79–64—During the execution of every 64-bit media instruction that writes a result to an MMX
register, the processor writes the result data to a 64-bit MMX register (the low 64 bits of the
associated 80-bit x87 floating-point physical register) and sets the exponent and sign bits (the high
16 bits of the associated 80-bit x87 floating-point physical register) to all 1s. In the x87
environment, the effect of setting the high 16 bits to all 1s indicates that the contents of the low 64
bits are not finite numbers. Such a designation prevents an x87 floating-point instruction from
interpreting the data as a finite x87 floating-point number.
register, the processor writes the result data to a 64-bit MMX register (the low 64 bits of the
associated 80-bit x87 floating-point physical register) and sets the exponent and sign bits (the high
16 bits of the associated 80-bit x87 floating-point physical register) to all 1s. In the x87
environment, the effect of setting the high 16 bits to all 1s indicates that the contents of the low 64
bits are not finite numbers. Such a designation prevents an x87 floating-point instruction from
interpreting the data as a finite x87 floating-point number.
The rest of the x87 floating-point processor state—the entire x87 control-word register, the remaining
fields of the status-word register, and the error pointers (instruction pointer, data pointer, and last
opcode register)—is not affected by the execution of 64-bit media instructions.
fields of the status-word register, and the error pointers (instruction pointer, data pointer, and last
opcode register)—is not affected by the execution of 64-bit media instructions.
The 2-bit tag fields defined by the x87 architecture for each x87 data register, and stored in the x87 tag-
word register (also called the floating-point tag word, or FTW), characterize the contents of the MMX
registers. The tag bits are visible to software only after an FSAVE or FNSAVE (but not FXSAVE)
instruction, as described in “Media and x87 Processor State” in Volume 2. Internally, however, the
processor maintains only a one-bit representation of each 2-bit tag field. This single bit indicates
whether the associated register is empty or full. Table 5-6 on page 233 shows the mapping between the
1-bit internal tag—which is referred to in this chapter by its empty or full state—and the 2-bit
architectural tag.
word register (also called the floating-point tag word, or FTW), characterize the contents of the MMX
registers. The tag bits are visible to software only after an FSAVE or FNSAVE (but not FXSAVE)
instruction, as described in “Media and x87 Processor State” in Volume 2. Internally, however, the
processor maintains only a one-bit representation of each 2-bit tag field. This single bit indicates
whether the associated register is empty or full. Table 5-6 on page 233 shows the mapping between the
1-bit internal tag—which is referred to in this chapter by its empty or full state—and the 2-bit
architectural tag.