AMD amd64 architecture User Manual
246
x87 Floating-Point Programming
AMD64 Technology
24592—Rev. 3.15—November 2009
Infinity Bit (Y).
Bit 12. This bit is obsolete. It can be read and written, but the value has no meaning.
On pre-386 processor implementations, the bit specified the affine (Y = 1) or projective (Y = 0)
infinity. The AMD64 architecture uses only the affine infinity, which specifies distinct positive and
negative infinity values.
infinity. The AMD64 architecture uses only the affine infinity, which specifies distinct positive and
negative infinity values.
6.2.4 x87 Tag Word Register (FTW)
The x87 tag word register contains a 2-bit tag field for each x87 physical data register. These tag fields
characterize the register’s data. Figure 6-5 shows the format of the tag word.
characterize the register’s data. Figure 6-5 shows the format of the tag word.
Figure 6-5.
x87 Tag Word Register (FTW)
In the memory image saved by the instructions described in “x87 Environment” on page 248, each x87
physical data register has two tag bits which are encoded according to the Tag Values shown in
Figure 6-5. Internally, the hardware may maintain only a single bit that indicates whether the
associated register is empty or full. The mapping between such a 1-bit internal tag and the 2-bit
software-visible architectural representation saved in memory is shown in Table 6-3 on page 246. In
such a mapping, whenever software saves the tag word, the processor expands the internal 1-bit tag
state to the 2-bit architectural representation by examining the contents of the x87 registers, as
described in “128-Bit, 64-Bit, and x87 Programming” in Volume 2.
physical data register has two tag bits which are encoded according to the Tag Values shown in
Figure 6-5. Internally, the hardware may maintain only a single bit that indicates whether the
associated register is empty or full. The mapping between such a 1-bit internal tag and the 2-bit
software-visible architectural representation saved in memory is shown in Table 6-3 on page 246. In
such a mapping, whenever software saves the tag word, the processor expands the internal 1-bit tag
state to the 2-bit architectural representation by examining the contents of the x87 registers, as
described in “128-Bit, 64-Bit, and x87 Programming” in Volume 2.
The FINIT and FNINIT instructions write the tag word so that it specifies all floating-point registers as
empty. Execution of 64-bit media instructions that write to an MMX™ register alter the tag bits by
empty. Execution of 64-bit media instructions that write to an MMX™ register alter the tag bits by
Table 6-3.
Mapping Between Internal and Software-Visible Tag Bits
Architectural State (Software-Visible)
Hardware State
State
Bit Value
Valid
00
Full
Zero
01
Special
(NaN, infinity, denormal, or unsupported)
(NaN, infinity, denormal, or unsupported)
10
Empty
11
Empty
9 8
7
6
5
4
3
2
1
0
10
11
12
13
14
15
TAG
(FPR6)
TAG
(FPR7)
TAG
(FPR4)
TAG
(FPR5)
TAG
(FPR2)
TAG
(FPR3)
TAG
(FPR0)
TAG
(FPR1)
Tag Values
00 = Valid
01 = Zero
10 = Special
11 = Empty
00 = Valid
01 = Zero
10 = Special
11 = Empty