AMD amd64 architecture User Manual
Overview of the AMD64 Architecture
3
24592—Rev. 3.15—November 2009
AMD64 Technology
1.1.2 Registers
Table 1-2 compares the register and stack resources available to application software, by operating
mode. The left set of columns shows the legacy x86 resources, which are available in the AMD64
architecture’s legacy and compatibility modes. The right set of columns shows the comparable
resources in 64-bit mode. Gray shading indicates differences between the modes. These register
differences (not including stack-width difference) represent the register extensions shown in
Figure 1-1.
mode. The left set of columns shows the legacy x86 resources, which are available in the AMD64
architecture’s legacy and compatibility modes. The right set of columns shows the comparable
resources in 64-bit mode. Gray shading indicates differences between the modes. These register
differences (not including stack-width difference) represent the register extensions shown in
Figure 1-1.
As Table 1-2 shows, the legacy x86 architecture (called legacy mode in the AMD64 architecture)
supports eight GPRs. In reality, however, the general use of at least four registers (EBP, ESI, EDI, and
ESP) is compromised because they serve special purposes when executing many instructions. The
AMD64 architecture’s addition of eight GPRs—and the increased width of these registers from 32 bits
to 64 bits—allows compilers to substantially improve software performance. Compilers have more
flexibility in using registers to hold variables. Compilers can also minimize memory traffic—and thus
boost performance—by localizing work within the GPRs.
supports eight GPRs. In reality, however, the general use of at least four registers (EBP, ESI, EDI, and
ESP) is compromised because they serve special purposes when executing many instructions. The
AMD64 architecture’s addition of eight GPRs—and the increased width of these registers from 32 bits
to 64 bits—allows compilers to substantially improve software performance. Compilers have more
flexibility in using registers to hold variables. Compilers can also minimize memory traffic—and thus
boost performance—by localizing work within the GPRs.
Table 1-2.
Application Registers and Stack, by Operating Mode
Register
or Stack
Legacy and Compatibility Modes
64-Bit Mode
1
Name
Number
Size (bits)
Name
Number
Size (bits)
General-Purpose
Registers (GPRs)
2
EAX, EBX, ECX,
EDX, EBP, ESI,
EDI, ESP
8
32
RAX, RBX, RCX,
RDX, RBP, RSI,
RDI, RSP,
R8–R15
16
64
256-bit YMM
Registers
Registers
YMM0–YMM7
8
256
YMM0–YMM15
16
256
128-Bit XMM
Registers
Registers
XMM0–XMM7
8
128
XMM0–XMM15
16
128
64-Bit MMX
Registers
Registers
MMX0–MMX7
3
8
64
MMX0–MMX7
3
8
64
x87 Registers
FPR0–FPR7
3
8
80
FPR0–FPR7
3
8
80
Instruction Pointer
2
EIP
1
32
RIP
1
64
Flags
2
EFLAGS
1
32
RFLAGS
1
64
Stack
—
16 or 32
—
64
Note:
1. Gray-shaded entries indicate differences between the modes. These differences (except stack-width difference) are
the AMD64 architecture’s register extensions.
2. This list of GPRs shows only the 32-bit registers. The 16-bit and 8-bit mappings of the 32-bit registers are also
accessible, as described in “Registers” on page 23.
3. The MMX0–MMX7 registers are mapped onto the FPR0–FPR7 physical registers, as shown in Figure 1-1. The x87
stack registers, ST(0)–ST(7), are the logical mappings of the FPR0–FPR7 physical registers.