AMD amd64 architecture User Manual
10
Memory Model
AMD64 Technology
24592—Rev. 3.15—November 2009
Figure 2-1.
Virtual-Memory Segmentation
Operating systems have used segmented memory as a method to isolate programs from the data they
used, in an effort to increase the reliability of systems running multiple programs simultaneously.
However, most modern operating systems do not use the segmentation features available in the legacy
x86 architecture. Instead, these operating systems handle segmentation functions entirely in software.
For this reason, the AMD64 architecture dispenses with most of the legacy segmentation functions in
64-bit mode. This allows 64-bit operating systems to be coded more simply, and it supports more
efficient management of multi-tasking environments than is possible in the legacy x86 architecture.
used, in an effort to increase the reliability of systems running multiple programs simultaneously.
However, most modern operating systems do not use the segmentation features available in the legacy
x86 architecture. Instead, these operating systems handle segmentation functions entirely in software.
For this reason, the AMD64 architecture dispenses with most of the legacy segmentation functions in
64-bit mode. This allows 64-bit operating systems to be coded more simply, and it supports more
efficient management of multi-tasking environments than is possible in the legacy x86 architecture.
2.1.2 Segment Registers
Segment registers hold the selectors used to access memory segments. Figure 2-2 on page 11 shows
the application-visible portion of the segment registers. In legacy and compatibility modes, all segment
registers are accessible to software. In 64-bit mode, only the CS, FS, and GS segments are recognized
by the processor, and software can use the FS and GS segment-base registers as base registers for
address calculation, as described in “FS and GS as Base of Address Calculation” on page 17. For
references to the DS, ES, or SS segments in 64-bit mode, the processor assumes that the base for each
of these segments is zero, neither their segment limit nor attributes are checked, and the processor
simply checks that all such addresses are in canonical form, as described in “64-Bit Canonical
Addresses” on page 15.
the application-visible portion of the segment registers. In legacy and compatibility modes, all segment
registers are accessible to software. In 64-bit mode, only the CS, FS, and GS segments are recognized
by the processor, and software can use the FS and GS segment-base registers as base registers for
address calculation, as described in “FS and GS as Base of Address Calculation” on page 17. For
references to the DS, ES, or SS segments in 64-bit mode, the processor assumes that the base for each
of these segments is zero, neither their segment limit nor attributes are checked, and the processor
simply checks that all such addresses are in canonical form, as described in “64-Bit Canonical
Addresses” on page 15.
513-107.eps
2
64
- 1
0
Base Address for
All Segments
Code Segment (CS) Base
Stack Segment (SS) Base
Data Segment (DS) Base
64-Bit Mode
(Flat Segmentation Model)
Legacy and Compatibility Mode
(Multi-Segment Model)
2
32
- 1
0
data
code
stack