AMD amd64 architecture User Manual
General-Purpose Programming
41
24592—Rev. 3.15—November 2009
AMD64 Technology
The AMD64 architecture does not impose data-alignment requirements for accessing data in memory.
However, depending on the location of the misaligned operand with respect to the width of the data bus
and other aspects of the hardware implementation (such as store-to-load forwarding mechanisms), a
misaligned memory access can require more bus cycles than an aligned access. For maximum
performance, avoid misaligned memory accesses.
However, depending on the location of the misaligned operand with respect to the width of the data bus
and other aspects of the hardware implementation (such as store-to-load forwarding mechanisms), a
misaligned memory access can require more bus cycles than an aligned access. For maximum
performance, avoid misaligned memory accesses.
Performance on many hardware implementations will benefit from observing the following operand-
alignment and operand-size conventions:
alignment and operand-size conventions:
•
Avoid misaligned data accesses.
•
Maintain consistent use of operand size across all loads and stores. Larger operand sizes
(doubleword and quadword) tend to make more efficient use of the data bus and any data-
forwarding features that are implemented by the hardware.
(doubleword and quadword) tend to make more efficient use of the data bus and any data-
forwarding features that are implemented by the hardware.
•
When using word or byte stores, avoid loading data from the same doubleword of memory, other
than the identical start addresses of the stores.
than the identical start addresses of the stores.
3.3
Instruction Summary
This section summarizes the functions of the general-purpose instructions. The instructions are
organized by functional group—such as, data-transfer instructions, arithmetic instructions, and so on.
Details on individual instructions are given in the alphabetically organized “General-PurposeInstruction Reference” in Volume 3.
organized by functional group—such as, data-transfer instructions, arithmetic instructions, and so on.
Details on individual instructions are given in the alphabetically organized “General-PurposeInstruction Reference” in Volume 3.
3.3.1 Syntax
Each instruction has a mnemonic syntax used by assemblers to specify the operation and the operands
to be used for source and destination (result) data. Figure 3-7 shows an example of the mnemonic
syntax for a compare (CMP) instruction. In this example, the CMP mnemonic is followed by two
operands, a 32-bit register or memory operand and an 8-bit immediate operand.
to be used for source and destination (result) data. Figure 3-7 shows an example of the mnemonic
syntax for a compare (CMP) instruction. In this example, the CMP mnemonic is followed by two
operands, a 32-bit register or memory operand and an 8-bit immediate operand.
Figure 3-7.
Mnemonic Syntax Example
513-139.eps
Mnemonic
First Source Operand
and Destination Operand
Second Source Operand
CMP reg/mem32, imm8