Nokia 9110 Service Manual
PAMS
Technical Documentation
RAE–2
BS1
Page 5 – 25
Section 02/99
Table 13. Spock CPU Controllable I/O Signals (continued)
LVDD
LVDD
Reset, Suspend
PDA LCD Logic
voltage activated
voltage activated
Routed to the Phaser
LVEE
LVEE
Reset, Suspend
PDA LCD bias
voltage activated
voltage activated
Routed to the Phaser
Memories
The memory units of the module are connected to the CPU via a 16–bit
wide data bus. Both memory types (DRAM and Flash) have an own
data– and address bus.
wide data bus. Both memory types (DRAM and Flash) have an own
data– and address bus.
XIP Flash 1
RFD Flash
XIP Flash 0
DRAM
SA [21:0]
SD [15:0]
MA [11:0]
MD [15:0]
control [3:0]
control [7:0]
BS1 CPU
DRAM memory
The 1Mx16bit DRAM is connected to the CPU with a dedicated 16–bit
wide data- and 12-bit wide address bus. The DRAM type used is the ex-
tended data out (EDO) DRAM with 60ns access time, and self–refresh
capability. DRAM is packaged in a 5.55mmX9.10mm, 40–ball uBGA
package.
wide data- and 12-bit wide address bus. The DRAM type used is the ex-
tended data out (EDO) DRAM with 60ns access time, and self–refresh
capability. DRAM is packaged in a 5.55mmX9.10mm, 40–ball uBGA
package.
When the DRAM is driven by the CPU, no wait states is needed.
Flash memory
Three 1Mx16bit Flash memory devices are used for non–volatile memory.
The Flash type features a 120ns access time. The Flash is packaged in
8mmX11mm 64–ball CSP package. When the Flash is read by the CPU,
4 wait states are needed to ensure proper timing.
The Flash type features a 120ns access time. The Flash is packaged in
8mmX11mm 64–ball CSP package. When the Flash is read by the CPU,
4 wait states are needed to ensure proper timing.