Nokia 9110 Service Manual
PAMS
Technical Documentation
RAE–2
BS1
Page 5 – 31
Section 02/99
Table 16. Testpoints
(continued)
Description /
Note
Note
Unit
Max
Nom
Min
Function
Name
I/O
Point
J403
I/O
MBUS
Bidirectional Serial Bus
2.30
2.80
2.85
VDC
High, to the
CMT
CMT
0
0.45
VDC
Low, to the
CMT
CMT
2.1
2.80
2.85
VDC
High, from the
CMT
CMT
0
0.5
VDC
Low, from the
CMT
CMT
J404
O
PWR_ONx
2.0
2.80
2.85
VDC
High
0
0.45
VDC
Low
J430
LF_INT
Intermidiate PLL loop filter
1.2
VDC
When PLLs are
locked
locked
J434
I
X32IN
1.35
VDC
High, Sini vawe
0
VDC
Low
J435
O
X32OUT
1.0
VDC
High
–0.3
VDC
Low
J440
ROMCS2
RFD flash chip select
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low, chip se-
lected
lected
J441
ROMCS0
XIP1 flash chip select
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low, chip se-
lected
lected
J442
FLASHWRx
XIP and RFD flashes write
bl
f
CPU
2.3
2.80
2.85
VDC
High
enable from CPU
0
0.45
VDC
Low, write en-
abled
abled
I
XIP and RFD flashes write
bl f
f
t
2.0
2.80
2.85
VDC
High
enable from frame connector
or testpads
0
0.8
VDC
Low, write en-
abled
abled
J443
ROMRDx
RFD flash read enable
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low, read en-
abled
abled
J444
WP
RFD flash write protect
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low, write pro-
tected
tected
J445
ROMCS1
XIP2 flash chip select
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low
J446
RASx
DRAM row address strobe
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low
J447
MWEx
DRAM write enable
2.3
2.80
2.85
VDC
High
0
0.45
VDC
Low
J448
CASL1x
DRAM upper column address
l
t
2.3
2.80
2.85
VDC
High
select
0
0.45
VDC
Low
J449
CASL0x
DRAM lower column address
l
t
2.3
2.80
2.85
VDC
High
select
0
0.45
VDC
Low
J450
FLASH_CTRL2
RFD flash status
2.4
2.80
2.85
VDC
High
0
0.4
VDC
Low