Nokia 9110 Service Manual
PAMS
Technical Documentation
RAE–2
BS8_RF
Page 3 – 12
Original 02/99
Frequency synthesizers
Both VCOs are locked with PLLs into stable frequency source, which is a
VCTCXO–module ( voltage controlled temperature compensated crystal
oscillator ). The VCTCXO is running at 13 MHz. Temperature effect is
controlled with AFC ( automatic frequency control ) voltage, the VCTCXO
is locked into the frequency of the base station. AFC is generated by
baseband with a 11 bit conventional DAC in COBBA.
VCTCXO–module ( voltage controlled temperature compensated crystal
oscillator ). The VCTCXO is running at 13 MHz. Temperature effect is
controlled with AFC ( automatic frequency control ) voltage, the VCTCXO
is locked into the frequency of the base station. AFC is generated by
baseband with a 11 bit conventional DAC in COBBA.
The UHF PLL is located in the SUMMA. There is 64/65 (P/P+1) prescal-
er, N– and A–divider, reference divider, phase detector and charge pump
for the external loop filter.
er, N– and A–divider, reference divider, phase detector and charge pump
for the external loop filter.
The UHF local signal is generated by a VCO–module ( VCO = voltage
controlled oscillator ) and sample of frequency of VCO is fed to prescaler.
The prescaler is a dual modulus divider. The output of the prescaler is
fed to the N– and A–dividers, which produce the input to phase detector.
controlled oscillator ) and sample of frequency of VCO is fed to prescaler.
The prescaler is a dual modulus divider. The output of the prescaler is
fed to the N– and A–dividers, which produce the input to phase detector.
The phase detector compares this signal to reference signal, which is di-
vided with reference divider from VCTCXO output. Output of the phase
detector is connected into charge pump, which charges or discharges in-
tegrator capacitor in the loop filter depending on the phase of the mea-
sured frequency compared to reference frequency.
vided with reference divider from VCTCXO output. Output of the phase
detector is connected into charge pump, which charges or discharges in-
tegrator capacitor in the loop filter depending on the phase of the mea-
sured frequency compared to reference frequency.
The loop filter filters out the pulses and generates the DC to control the
frequency of UHF–VCO. The loop filter defines step response of the PLL
( settling time ) and effects to stability of the loop, that’s why integrator ca-
pacitor has got a resistor for phase compensation.
frequency of UHF–VCO. The loop filter defines step response of the PLL
( settling time ) and effects to stability of the loop, that’s why integrator ca-
pacitor has got a resistor for phase compensation.
The other filter components are for sideband rejection. Dividers are con-
trolled via serial bus. SDATA is for data, SCLK is serial clock for the bus
and SENA1 is a latch enable, which stores new data into dividers. The
UHF–synthesizer is the channel synthesizer, so the channel spacing is
200 kHz. 200 kHz is the reference frequency for the phase detector.
trolled via serial bus. SDATA is for data, SCLK is serial clock for the bus
and SENA1 is a latch enable, which stores new data into dividers. The
UHF–synthesizer is the channel synthesizer, so the channel spacing is
200 kHz. 200 kHz is the reference frequency for the phase detector.